Reduction of process monitoring in semiconductor chip manufacturing
Author(s)Amar, Ajay, 1964-
Arnold Barnett and Duane Boning.
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This thesis concerns in-line inspection scheduling policies in semiconductor chip manufacturing. Intel uses extensive monitoring (inspections) in the manufacturing process. While the inspections help safeguard process stability and boost manufacturing yield, they also account for a substantial fraction of the company's variable manufacturing costs. Intel is under pressure to cut inspections as a means of lowering these costs, and is currently pursuing an aggressive reduction policy. This thesis examines the risks and benefits of inspection reduction, and identifies competing considerations that affect the decision of how much inspection is appropriate. It proposes a decision algorithm to evaluate current inspection levels and determine the optimal frequency of inspections.
Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (leaf 40).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Sloan School of Management
Massachusetts Institute of Technology
Sloan School of Management, Electrical Engineering and Computer Science