2026-09-19T03:29:06Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1014712022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anantha P. Chandrakasan.
Duan, Chuhong
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2016-03-03T20:30:34Z
2016-03-03T20:30:34Z
2015
2015
http://hdl.handle.net/1721.1/101471
940970663
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 97-100).
The binary values processed and stored at the intermediary stages of an algorithm are often highly correlated. Motivated in part by this observation and the ever-increasing challenge of power density for Integrated Circuit (IC) systems, a novel reconfigurable memory framework is proposed in this thesis which builds upon traditional low power techniques such as voltage scaling in order to achieve up to 31% power savings for targeted applications. The general strategy underlying the presented low power memory innovation is to leverage global and local data correlation in order to make predictions so that the overall switching activity on the read bit-lines of the Static Random Access Memory (SRAM) is reduced with minimal area overhead. Additionally, multiple prediction schemes are incorporated into this framework wherein statistical data features are used to optimally configure each column of the proposed SRAM. Analysis tools for developing this type of reconfigurable low-power memories are provided. An example reconfigurable CP SRAM adhering to the proposed framework is presented which includes the novel designs of a 10-transistor (10T) bit-cell, a prediction-based conditional pre-charge scheme, and a column-wise reconfigurable dual prediction mode architecture. A 16kbit SRAM incorporating these innovations is implemented in a test chip using a 28nm FD-SOI CMOS process. Using post-layout simulations, the proposed SRAM is found to provide 14%-20%, 4%, and 31% reductions in read power as compared with a conventional 8T SRAM for three targeted applications: the coefficient SRAMs in a sparse Fast Fourier Transform (sFFT) implementation, the Support Vector Machine (SVM) weights SRAM in an objection detection system, and the Motion Estimation (ME) reference pixel SRAM in a video coding system, respectively.
by Chuhong Duan.
S.M.
100 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Energy efficient reconfigurable SRAM using data-dependency
Thesis
application/pdf
Publication
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<Abstract>The binary values processed and stored at the intermediary stages of an algorithm are often highly correlated. Motivated in part by this observation and the ever-increasing challenge of power density for Integrated Circuit (IC) systems, a novel reconfigurable memory framework is proposed in this thesis which builds upon traditional low power techniques such as voltage scaling in order to achieve up to 31% power savings for targeted applications. The general strategy underlying the presented low power memory innovation is to leverage global and local data correlation in order to make predictions so that the overall switching activity on the read bit-lines of the Static Random Access Memory (SRAM) is reduced with minimal area overhead. Additionally, multiple prediction schemes are incorporated into this framework wherein statistical data features are used to optimally configure each column of the proposed SRAM. Analysis tools for developing this type of reconfigurable low-power memories are provided. An example reconfigurable CP SRAM adhering to the proposed framework is presented which includes the novel designs of a 10-transistor (10T) bit-cell, a prediction-based conditional pre-charge scheme, and a column-wise reconfigurable dual prediction mode architecture. A 16kbit SRAM incorporating these innovations is implemented in a test chip using a 28nm FD-SOI CMOS process. Using post-layout simulations, the proposed SRAM is found to provide 14%-20%, 4%, and 31% reductions in read power as compared with a conventional 8T SRAM for three targeted applications: the coefficient SRAMs in a sparse Fast Fourier Transform (sFFT) implementation, the Support Vector Machine (SVM) weights SRAM in an objection detection system, and the Motion Estimation (ME) reference pixel SRAM in a video coding system, respectively.</Abstract>
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