2026-09-19T07:26:27Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1060712022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Jack B. Dennis.
Zhou, Mo, S.M. Massachusetts Institute of Technology
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2016-12-22T16:27:46Z
2016-12-22T16:27:46Z
2016
2016
http://hdl.handle.net/1721.1/106071
965197436
Thesis: S.M. in Computer Science and Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 53-54).
This thesis research is a study of a novel processor architecture for a massively parallel computer system. An existing simulation of the Fresh Breeze architecture has been extended to incorporate a multi-level memory hierarchy and dynamic load balancing. An efficient hardware-based garbage collection mechanism has been proposed. Various design trade-offs are evaluated. The simulation demonstrates that the architecture can support memory access with DRAM latency and still achieve high processor utilization.
by Mo Zhou.
S.M. in Computer Science and Engineering
54 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Simulation of a novel multiprocessor system based on dataflow principles
Thesis
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