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Anantha P. Chandrakasan. Orguc, Sirma Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2016-12-22T16:28:23Z 2016-12-22T16:28:23Z 2016 2016 http://hdl.handle.net/1721.1/106085 965294053 Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016. Cataloged from PDF version of thesis. Includes bibliographical references (pages 109-112). Miniaturized sensor nodes have a very tight power budget, especially in the case of implantables and health monitoring devices that require long operation lifetime. Exploiting low-voltage techniques in analog design can enable further power savings, which has not been explored much. However, for conventional analog-front-end (AFE) topologies, voltage scaling could potentially bring several limitations to the important performance metrics such as the linearity, robustness and the power-efficiency. This thesis work describes the design of a 0.3V biopotential sensor interface for stress monitoring applications, which achieves state-of-the-art power-efficiency, and ensures enough circuit reliability with reduced dynamic range requirement. The proposed sensor interface consists of an amplifier and an analog-to-digital converter (ADC). The simulated amplifier achieves 0.95nW power consumption with a power-efficiency-factor (PEF) of 1.57. With this power budget, the amplifier also presents large signal cancellation capability in order to reject the motion artifacts. The system, together with the ADC consumes 4.1nW power, and has an area of 0.2mm2 which makes the sensor interface suitable for wearable and implantable devices. The chip has been submitted for fabrication in a low power 65nm digital CMOS process, and the simulation results are presented. by Sirma Orguc. S.M. 112 pages eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. 0.3V biopotential sensor interface for stress monitoring Zero point three volt biopotential sensor interface for stress monitoring Thesis application/pdf Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="6cbe2df4-d594-42a7-9932-b99a8ea864d8"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>0.3V biopotential sensor interface for stress monitoring</Title> <Subtitle>Zero point three volt biopotential sensor interface for stress monitoring</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2016</PublicationDate> <Authors> <Author> <DisplayName>Orguc, Sirma</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>Miniaturized sensor nodes have a very tight power budget, especially in the case of implantables and health monitoring devices that require long operation lifetime. Exploiting low-voltage techniques in analog design can enable further power savings, which has not been explored much. However, for conventional analog-front-end (AFE) topologies, voltage scaling could potentially bring several limitations to the important performance metrics such as the linearity, robustness and the power-efficiency. This thesis work describes the design of a 0.3V biopotential sensor interface for stress monitoring applications, which achieves state-of-the-art power-efficiency, and ensures enough circuit reliability with reduced dynamic range requirement. The proposed sensor interface consists of an amplifier and an analog-to-digital converter (ADC). The simulated amplifier achieves 0.95nW power consumption with a power-efficiency-factor (PEF) of 1.57. With this power budget, the amplifier also presents large signal cancellation capability in order to reject the motion artifacts. The system, together with the ADC consumes 4.1nW power, and has an area of 0.2mm2 which makes the sensor interface suitable for wearable and implantable devices. The chip has been submitted for fabrication in a low power 65nm digital CMOS process, and the simulation results are presented.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>