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Cardinal Warde. Tadele, Wegene Haile Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2017-01-30T19:16:12Z 2017-01-30T19:16:12Z 2015 2015 http://hdl.handle.net/1721.1/106739 969343851 Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. Cataloged from PDF version of thesis. Pages 7 and 8 are missing. Includes bibliographical references (pages 99-103). The Compact Integrated Optoelectronic Neural (COIN) Co-processor, a prototype of artificial neural network implemented in hybrid optics and optoelectronic hardware, aims to implement a multi-layer neural network algorithm by performing parallel and efficient neural computations. In this thesis, we design and implement optoelectronic thresholding (activation), weighting and memory circuits for the COIN processor. The first version involved the design of fixed thresholding and weighting functions. The second version incorporated a local capacitive memory element as well as variable weighting schemes. The third version introduces an additional flexibility for variable thresholding by changing the bias voltages of control transistors. A 9x9 array of proof of concept printed circuit board (PCB) with an area of 4.5x 4.5 in² and total power consumption of 1.37W was designed and tested for version-I optoelectronic neuron architecture. A spice simulation was performed for the last two versions for integrated circuit (IC) implementation. The work developed in this thesis provides some guidance on the design of optoelectronic neural activation function for the realization of the embodiment of the fully integrated COIN Co-processor to be built in the future. by Wegene Haile Tadele. M.Eng. 103 pages eng Massachusetts Institute of Technology MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Design of optoelectronic activation, local memory and weighting circuits for Compact Integrated Optoelectronic Neural (COIN) Co-processor Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="9bf83f38-fe75-4bb1-bdde-007c209000b2"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Design of optoelectronic activation, local memory and weighting circuits for Compact Integrated Optoelectronic Neural (COIN) Co-processor</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2015</PublicationDate> <Authors> <Author> <DisplayName>Tadele, Wegene Haile</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>The Compact Integrated Optoelectronic Neural (COIN) Co-processor, a prototype of artificial neural network implemented in hybrid optics and optoelectronic hardware, aims to implement a multi-layer neural network algorithm by performing parallel and efficient neural computations. In this thesis, we design and implement optoelectronic thresholding (activation), weighting and memory circuits for the COIN processor. The first version involved the design of fixed thresholding and weighting functions. The second version incorporated a local capacitive memory element as well as variable weighting schemes. The third version introduces an additional flexibility for variable thresholding by changing the bias voltages of control transistors. A 9x9 array of proof of concept printed circuit board (PCB) with an area of 4.5x 4.5 in² and total power consumption of 1.37W was designed and tested for version-I optoelectronic neuron architecture. A spice simulation was performed for the last two versions for integrated circuit (IC) implementation. The work developed in this thesis provides some guidance on the design of optoelectronic neural activation function for the realization of the embodiment of the fully integrated COIN Co-processor to be built in the future.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>