2026-09-20T21:59:26Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/106992022-01-14T21:41:38Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Chiu, Angela Lan
Massachusetts Institute of Technology. Laboratory for Information and Decision Systems.
Massachusetts Institute of Technology. Laboratory for Information and Decision Systems
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-08-18T17:54:12Z
2005-08-18T17:54:12Z
1997
2382
http://hdl.handle.net/1721.1/10699
36598377
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
Includes bibliographical references (p. 89-92).
Supported by the U.S. Army Research Office. ARO ASSERT DAAH04-94-G-0221 Supported by National Science Foundation. NCR-92036379 Supported by Advanced Research Project Agency. MDA972-92-J-1038
Chiu, A.L.
Ph.D.
92 p.
4619469 bytes
4619227 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology, Laboratory for Information and Decision Systems
Massachusetts Institute of Technology
LIDS-P ; 2382.
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Laboratory for Information and Decision Systems.
TK7855.M41 E3845 no.2382
Full utilization, fairness, and access delay on high speed slotted bus networks
Thesis
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