2026-09-19T14:27:25Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1119172022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anantha P. Chandrakasan and Hae-Seung Lee.
Jeong, Taehoon
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2017-10-18T15:09:56Z
2017-10-18T15:09:56Z
2017
2017
http://hdl.handle.net/1721.1/111917
1005701141
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 65-68).
Designing a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology and is currently being fabricated.
by Taehoon Jeong.
S.M.
68 pages
eng
Massachusetts Institute of Technology
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A pipelined analog-to-digital converter with low-gain, low-bandwidth op-amps
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="d70f6ae8-194c-4dc4-bf59-2ad73f5f1bc3">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>A pipelined analog-to-digital converter with low-gain, low-bandwidth op-amps</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2017</PublicationDate>
<Authors>
<Author>
<DisplayName>Jeong, Taehoon</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>Designing a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology and is currently being fabricated.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>