<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T05:39:51Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/113963" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/113963</identifier><datestamp>2023-07-06T16:04:35Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131023</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Ruonan Han.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Zhang, Guo (Electrical and computer science engineer) Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department" lang="en_US">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2018-03-02T22:20:48Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2018-03-02T22:20:48Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2017</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2017</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">http://hdl.handle.net/1721.1/113963</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">1023498531</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Cataloged from PDF version of thesis.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (pages 47-49).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">The topic covered by this thesis is the project of designing a terahertz imager chip on nowadays commercialized mature silicon platform. In the project, we developed the design method of a multi-functional heterodyne pixel and a scalable array architecture. The pixel is a compact electromagnetic structure simultaneously performs voltage-controlled 140 GHz local oscillation, 280-GHz-signal receiving, sub-harmonic mixing, and intermediate frequency (IF) signal extraction. Each pixel consumes 10 mW power and achieves a sensitivity of 2.9 pW in simulation. The local oscillator (LO) of the pixel is phase coupled with its neighbors; the whole oscillator array is then stabilized by an on-chip THz phase-locked loop. This architecture gives excellent array scalability. First, the LO power is evenly distributed and does not degrade in a larger array scale as a normal centralized array does. Second, the phase noise of the coupled LO network improves linearly with the array size. The simulated phase noise at 1-MHz frequency offset is -90 dBc/Hz for an 8 x 8 array and -101 dBc/Hz for a 32 x 32 array. This chip is capable of digital beam steering, too. The first version of the chip prototype with a 10 x 10 array is fabricated using a 130-nm SiGe BiCMOS process and tested.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Guo Zhang.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">S.M.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">49 pages</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso" lang="en_US">eng</dim:field>
   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri" lang="en_US">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Terahertz beam-steering imager using a scalable 2D-coupled architecture and multi- functional heterodyne pixels</dim:field>
   <dim:field mdschema="dc" element="type" lang="en_US">Thesis</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="mimetype">application/pdf</dim:field>
   <dim:field mdschema="dspace" element="authorsordered">false</dim:field>
   <dim:field mdschema="dspace" element="entity" qualifier="type">Publication</dim:field>
   <dim:field mdschema="others" element="access-status">unknown</dim:field>
   <dim:field mdschema="others" element="access-status">unknown</dim:field>
   <dim:field mdschema="cerif" element="openaire" authority="" confidence="-1">&lt;Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="2f48a5fa-034a-47ec-9811-9bda8a220641">
	&lt;Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843&lt;/Type>
	&lt;Language>eng&lt;/Language>
   	&lt;Title>Terahertz beam-steering imager using a scalable 2D-coupled architecture and multi- functional heterodyne pixels&lt;/Title>
   	&lt;PublishedIn>
    	&lt;Publication>
      	&lt;/Publication>
   	&lt;/PublishedIn>
   	&lt;PublicationDate>2017&lt;/PublicationDate>
   	&lt;Authors>
      	&lt;Author>
        	&lt;DisplayName>Zhang, Guo (Electrical and computer science engineer) Massachusetts Institute of Technology&lt;/DisplayName>
         	&lt;Affiliation>
         		&lt;OrgUnit>
         		&lt;/OrgUnit>
         	&lt;/Affiliation>
      	&lt;/Author>
	&lt;/Authors>
   	&lt;Editors>
	&lt;/Editors>
    &lt;Publishers>
        &lt;Publisher>
            &lt;DisplayName>Massachusetts Institute of Technology&lt;/DisplayName>
            &lt;OrgUnit />
        &lt;/Publisher>
    &lt;/Publishers>
    &lt;License>http://dspace.mit.edu/handle/1721.1/7582&lt;/License>
    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>The topic covered by this thesis is the project of designing a terahertz imager chip on nowadays commercialized mature silicon platform. In the project, we developed the design method of a multi-functional heterodyne pixel and a scalable array architecture. The pixel is a compact electromagnetic structure simultaneously performs voltage-controlled 140 GHz local oscillation, 280-GHz-signal receiving, sub-harmonic mixing, and intermediate frequency (IF) signal extraction. Each pixel consumes 10 mW power and achieves a sensitivity of 2.9 pW in simulation. The local oscillator (LO) of the pixel is phase coupled with its neighbors; the whole oscillator array is then stabilized by an on-chip THz phase-locked loop. This architecture gives excellent array scalability. First, the LO power is evenly distributed and does not degrade in a larger array scale as a normal centralized array does. Second, the phase noise of the coupled LO network improves linearly with the array size. The simulated phase noise at 1-MHz frequency offset is -90 dBc/Hz for an 8 x 8 array and -101 dBc/Hz for a 32 x 32 array. This chip is capable of digital beam steering, too. The first version of the chip prototype with a 10 x 10 array is fabricated using a 130-nm SiGe BiCMOS process and tested.&lt;/Abstract>
	&lt;Access xmlns="http://purl.org/coar/access_right" 
    >
    &lt;/Access>
&lt;/Publication>
</dim:field>
</dim:dim>
</metadata></record></GetRecord></OAI-PMH>