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Tomás Palacios. Piedra, Daniel, Ph. D. Massachusetts Institute of Technology Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2018-05-23T16:34:08Z 2018-05-23T16:34:08Z 2018 2018 http://hdl.handle.net/1721.1/115772 1036987593 Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018. Cataloged from PDF version of thesis. Includes bibliographical references. As silicon devices approach their intrinsic material and technological limit, there is an opportunity for alternative semiconductor materials to push the performance of electronics forward. Gallium nitride (GaN) has demonstrated very promising performance for advanced electronics, but there is still room for improvement. This thesis discusses several new transistor designs to improve the performance of GaN-based power devices as well as demonstrations of their scaling potential and integration capability with silicon. Specifically, we have developed a wide-periphery GaN fin-based high electron mobility transistor process for power switching. The process was developed with emphasis on the passivation, field plates, gate periphery scaling, and packaging. A CMOS compatible GaN processing technology on 200-mm wafers was developed and optimized, with particular attention focused on the recess etching through the wide-bandgap AlGaN barrier to reduce the contact resistance. A study of a heterogeneous integration technology to integrate GaN and Si devices was conducted. This involved an approach to monolithically integrate GaN and Si devices which used a bonded SOI wafer with a Si (111) substrate and Si (100) device layer with windows opened to access the (111) layer to selectively grow GaN. Characterization of the transistor properties in GaN windows of different sizes was performed to qualify the optimal window size for power devices in future integrated systems. by Daniel Piedra. Ph.D. 130 pages eng Massachusetts Institute of Technology MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Design-space and scalable technology for GaN based power transistors Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="a791f60b-d684-4079-8af7-ac8a4362188b"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Design-space and scalable technology for GaN based power transistors</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2018</PublicationDate> <Authors> <Author> <DisplayName>Piedra, Daniel, Ph. D. Massachusetts Institute of Technology</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>As silicon devices approach their intrinsic material and technological limit, there is an opportunity for alternative semiconductor materials to push the performance of electronics forward. Gallium nitride (GaN) has demonstrated very promising performance for advanced electronics, but there is still room for improvement. This thesis discusses several new transistor designs to improve the performance of GaN-based power devices as well as demonstrations of their scaling potential and integration capability with silicon. Specifically, we have developed a wide-periphery GaN fin-based high electron mobility transistor process for power switching. The process was developed with emphasis on the passivation, field plates, gate periphery scaling, and packaging. A CMOS compatible GaN processing technology on 200-mm wafers was developed and optimized, with particular attention focused on the recess etching through the wide-bandgap AlGaN barrier to reduce the contact resistance. A study of a heterogeneous integration technology to integrate GaN and Si devices was conducted. This involved an approach to monolithically integrate GaN and Si devices which used a bonded SOI wafer with a Si (111) substrate and Si (100) device layer with windows opened to access the (111) layer to selectively grow GaN. Characterization of the transistor properties in GaN windows of different sizes was performed to qualify the optimal window size for power devices in future integrated systems.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>