2026-09-19T02:43:19Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1197732026-06-06T00:54:42Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Arvind and Beth Markey.
Rodriguez Gallegos, Juan Miguel
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2018-12-18T20:04:03Z
2018-12-18T20:04:03Z
2018
2018
http://hdl.handle.net/1721.1/119773
1078637854
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 32-33).
The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system.
by Juan Miguel Rodriguez Gallegos.
M.Eng.
33 pages
eng
Massachusetts Institute of Technology
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A user interface for algorithmic debug
Thesis
application/pdf
Publication
unknown
unknown
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<Abstract>The hardware verification pipeline for server-scale system on chips (SoCs) is as complex as the SoCs themselves. Intel's Validation Acceleration through Shared Expertise (VASE) tool allows teams at different stages of the verification pipeline-from subsystem development to system integration-to share key architectural, test, and debug knowledge. By enabling system experts to automate the detection of common simulation failures, VASE allows the engineers who are inheriting a subsystem to instantly have access to their expertise whenever a simulation failure occurs. The VASE tool has the potential to greatly increase validation efficiency, but its adoption into Intel's verification work flow is put at risk by usability issues. To address these shortcomings, I developed a user interface that facilitates the creation of the simulation failure debug decision trees by the system experts. This GUI aims to increase usability for tree definition and manipulation, to enforce node subtree coherence across all trees, and to provide a tree building solution which scales with the complexity of the system.</Abstract>
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