<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-18T21:15:46Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/119915" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/119915</identifier><datestamp>2026-06-06T00:55:31Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131023</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Julian Shun.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Yang, Mengjiao</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2019-01-11T15:06:02Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2019-01-11T15:06:02Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2018</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2018</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">http://hdl.handle.net/1721.1/119915</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">1080643331</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">This electronic version was submitted by the student author.  The certified thesis is available in the Institute Archives and Special Collections.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Cataloged from student-submitted PDF version of thesis.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (pages 63-67).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">High-performance graph processing is challenging because the sizes and structures of real-world graphs can vary widely. Graph algorithms also have distinct performance characteristics that lead to different performance bottlenecks. Even though memory technologies such as CPU cache and non-uniform memory access (NUMA) have been designed to improve software performance, the existing graph processing frameworks either do not take advantage of these hardware features or over-complicate the original graph algorithms. In addition, these frameworks do not provide an interface for easily composing and fine-tuning performance optimizations from various levels of the software stack. As a result, they achieve suboptimal performance. The work described in this thesis builds on recent research in developing a domain-specific language (DSL) for graph processing. GraphIt is a DSL designed to provide a comprehensive set of performance optimizations and an interface to combine the best optimization schedules. This work extends the GraphIt DSL to support locality optimizations on modern multisocket multicore machines, while preserving the simplicity of graph algorithms. To our knowledge, this is the first work to support cache and NUMA optimizations in a graph DSL. We show that cache and NUMA optimizations together are able to improve the performance of GraphIt by up to a factor of 3. Combined with all of the optimizations in GraphIt, our performance is up to 4.8x faster than the next fastest existing framework. In addition, algorithms implemented in GraphIt use fewer lines of code than existing frameworks. The work in this thesis supports the design choice of a compiler approach to constructing graph processing systems. The high performance and simplicity of GraphIt justify the separation of concerns (modularity) design principle in computer science, and contribute to the larger effort of agile software systems development.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Mengjiao Yang.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">M.Eng.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">67 pages</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso" lang="en_US">eng</dim:field>
   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri" lang="en_US">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Cache and NUMA optimizations in a domain-specific language for graph processing</dim:field>
   <dim:field mdschema="dc" element="title" qualifier="alternative" lang="en_US">Cache and non-uniform memory access optimizations in a domain-specific language for graph processing</dim:field>
   <dim:field mdschema="dc" element="type" lang="en_US">Thesis</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="mimetype">application/pdf</dim:field>
   <dim:field mdschema="dspace" element="authorsordered">false</dim:field>
   <dim:field mdschema="dspace" element="entity" qualifier="type">Publication</dim:field>
   <dim:field mdschema="others" element="access-status">unknown</dim:field>
   <dim:field mdschema="others" element="access-status">unknown</dim:field>
   <dim:field mdschema="cerif" element="openaire" authority="" confidence="-1">&lt;Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="af75eed1-236d-46db-94c2-bc60d60b8a5f">
	&lt;Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843&lt;/Type>
	&lt;Language>eng&lt;/Language>
   	&lt;Title>Cache and NUMA optimizations in a domain-specific language for graph processing&lt;/Title>
   	&lt;Subtitle>Cache and non-uniform memory access optimizations in a domain-specific language for graph processing&lt;/Subtitle>
   	&lt;PublishedIn>
    	&lt;Publication>
      	&lt;/Publication>
   	&lt;/PublishedIn>
   	&lt;PublicationDate>2018&lt;/PublicationDate>
   	&lt;Authors>
      	&lt;Author>
        	&lt;DisplayName>Yang, Mengjiao&lt;/DisplayName>
         	&lt;Affiliation>
         		&lt;OrgUnit>
         		&lt;/OrgUnit>
         	&lt;/Affiliation>
      	&lt;/Author>
	&lt;/Authors>
   	&lt;Editors>
	&lt;/Editors>
    &lt;Publishers>
        &lt;Publisher>
            &lt;DisplayName>Massachusetts Institute of Technology&lt;/DisplayName>
            &lt;OrgUnit />
        &lt;/Publisher>
    &lt;/Publishers>
    &lt;License>http://dspace.mit.edu/handle/1721.1/7582&lt;/License>
    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>High-performance graph processing is challenging because the sizes and structures of real-world graphs can vary widely. Graph algorithms also have distinct performance characteristics that lead to different performance bottlenecks. Even though memory technologies such as CPU cache and non-uniform memory access (NUMA) have been designed to improve software performance, the existing graph processing frameworks either do not take advantage of these hardware features or over-complicate the original graph algorithms. In addition, these frameworks do not provide an interface for easily composing and fine-tuning performance optimizations from various levels of the software stack. As a result, they achieve suboptimal performance. The work described in this thesis builds on recent research in developing a domain-specific language (DSL) for graph processing. GraphIt is a DSL designed to provide a comprehensive set of performance optimizations and an interface to combine the best optimization schedules. This work extends the GraphIt DSL to support locality optimizations on modern multisocket multicore machines, while preserving the simplicity of graph algorithms. To our knowledge, this is the first work to support cache and NUMA optimizations in a graph DSL. We show that cache and NUMA optimizations together are able to improve the performance of GraphIt by up to a factor of 3. Combined with all of the optimizations in GraphIt, our performance is up to 4.8x faster than the next fastest existing framework. In addition, algorithms implemented in GraphIt use fewer lines of code than existing frameworks. The work in this thesis supports the design choice of a compiler approach to constructing graph processing systems. The high performance and simplicity of GraphIt justify the separation of concerns (modularity) design principle in computer science, and contribute to the larger effort of agile software systems development.&lt;/Abstract>
	&lt;Access xmlns="http://purl.org/coar/access_right" 
    >
    &lt;/Access>
&lt;/Publication>
</dim:field>
</dim:dim>
</metadata></record></GetRecord></OAI-PMH>