2026-09-20T13:24:59Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1204062022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Karl K. Berggren.
Butters, Brenden A
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2019-02-14T15:48:45Z
2019-02-14T15:48:45Z
2018
2018
http://hdl.handle.net/1721.1/120406
1083768766
Thesis: S.M. in Computer Science, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 213-215).
Superconducting computers promise very high computation speeds while also consuming far less power than their conventional counterparts. However, much of the progress in this field has been stymied by the lack of a scalable superconducting memory technology. In this thesis, I present the design of, and demonstrate the operation of, a superconducting nanowire-based memory cell. In contrast to existing designs, this cell operates by means of kinetic rather than geometric inductance. Thus, the cell size can be made much smaller than would otherwise be possible. With the successful operation of the single cell, paths to larger arrays are explored, and a small array demonstrated. The further development of the technology demonstrated in this work will allow for the production of large-scale superconducting processors, and the eventual development of superconducting supercomputers.
by Brenden A. Butters.
S.M. in Computer Science
215 pages
eng
Massachusetts Institute of Technology
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Development of a scalable superconducting memory
Thesis
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