2026-09-18T20:36:28Zhttps://dspace.mit.edu/server/oai/request

oai:dspace.mit.edu:1721.1/1226932021-07-05T14:03:20Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023

Max M. Shulaker and Anantha P. Chandrakasan. Amer, Aya G.(Aya Galal Mahdy ElSayed) Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2019-11-04T19:53:36Z 2019-11-04T19:53:36Z 2019 2019 https://hdl.handle.net/1721.1/122693 1124852442 This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019 Cataloged from student-submitted PDF version of thesis. Includes bibliographical references (pages 49-50). Next-generation applications require processing on massive amount of data in real-time, exceeding the capabilities of electronic systems today. This has spurred research in a wide-range of areas: from new devices to replace silicon-based field-effect transistors (FETs) to new circuit and system architectures with fine-grained and dense integration of logic and memory. However, isolated improvements in just one area is insufficient. Rather, enabling these next-generation applications will require combining benefits across all levels of the computing stack: leveraging new devices to realize new circuits and architectures. For instance, carbon nanotube (CNT) field-effect transistors (CNFETs) for logic and Resistive Random-Access Memory (RRAM) for memory are two promising emerging nanotechnologies for energy-efficient electronics. However, CNFETs suffer from inherent imperfections (such as of metallic CNTs, m-CNTs), which have prohibited realizing large-scale CNFET circuits in the past. This work proposes a circuit design technique that integrates and combines the benefits of both CNFETs with RRAM to realize three-dimensional (3D) circuits that are immune to m-CNTs. Leveraging this technique, we show the first experimental demonstration of CNFET-based analog mixed-signal circuits. by Aya G. Amer. S.M. S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science 50 pages eng Massachusetts Institute of Technology MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. SHARC : self-healing analog with RRAM and CNFETs Thesis application/pdf 2019-11-04T19:53:34Z Publication Master EECS unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="978b1c60-63a6-4075-9e0e-82fe8483dcbc"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>SHARC : self-healing analog with RRAM and CNFETs</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2019</PublicationDate> <Authors> <Author> <DisplayName>Amer, Aya G.(Aya Galal Mahdy ElSayed)</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>Next-generation applications require processing on massive amount of data in real-time, exceeding the capabilities of electronic systems today. This has spurred research in a wide-range of areas: from new devices to replace silicon-based field-effect transistors (FETs) to new circuit and system architectures with fine-grained and dense integration of logic and memory. However, isolated improvements in just one area is insufficient. Rather, enabling these next-generation applications will require combining benefits across all levels of the computing stack: leveraging new devices to realize new circuits and architectures. For instance, carbon nanotube (CNT) field-effect transistors (CNFETs) for logic and Resistive Random-Access Memory (RRAM) for memory are two promising emerging nanotechnologies for energy-efficient electronics. However, CNFETs suffer from inherent imperfections (such as of metallic CNTs, m-CNTs), which have prohibited realizing large-scale CNFET circuits in the past. This work proposes a circuit design technique that integrates and combines the benefits of both CNFETs with RRAM to realize three-dimensional (3D) circuits that are immune to m-CNTs. Leveraging this technique, we show the first experimental demonstration of CNFET-based analog mixed-signal circuits.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>