2026-09-19T19:13:04Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1230202026-06-06T00:48:50Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Alec J. Poitzsch and Ruonan Han.
Estay Forno, Ignacio.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2019-11-22T00:02:41Z
2019-11-22T00:02:41Z
2019
2019
https://hdl.handle.net/1721.1/123020
1127640115
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (page 95).
This thesis is focused around the development of an amplifier with novel features in a 200 V silicon process internal to Analog Devices. Despite being on a closed-process, the discussion focuses on topological and architectural developments that are applicable to a wide range of high voltage processes. The use case examined is one whereby large capacitive loads need to be driven by high voltage analog steps anywhere in a 200 V range, with ideal slew rates measuring in the kV/s range, while having clean, adjustable current limiting and low quiescent current consumption. Several common amplifier topologies are examined, with their merits and drawbacks discussed in the context of the use case. Ultimately, a hybridized approach is taken for an input stage for the amplifier that accomplishes high slew rates at the output while maintaining accurate, adjustable current limiting. The amplifier discussed, designed, and simulated operates at a 200 V rail-to-rail potential, with up to 1 A of continuous output current, with a slew rate exceeding 1 kV/s, drawing only 25 mA quiescent, and user-adjustable current limiting that operates without the need for an inefficient in-line current-sense resistor. The current limiting blocks discussed operate with a no excess DC current or power to operate apart from a small amount supplied for current-limiting adjustability.
by Ignacio Estay Forno.
M.Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
95 pages
eng
Massachusetts Institute of Technology
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Design and analysis of a 200 volt, high slew rate, current-limited operational amplifier
Thesis
application/pdf
2019-11-22T00:02:41Z
Publication
Master
EECS
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="1323bbb7-1cce-48e2-ba96-12bc3c693eee">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>Design and analysis of a 200 volt, high slew rate, current-limited operational amplifier</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2019</PublicationDate>
<Authors>
<Author>
<DisplayName>Estay Forno, Ignacio.</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>This thesis is focused around the development of an amplifier with novel features in a 200 V silicon process internal to Analog Devices. Despite being on a closed-process, the discussion focuses on topological and architectural developments that are applicable to a wide range of high voltage processes. The use case examined is one whereby large capacitive loads need to be driven by high voltage analog steps anywhere in a 200 V range, with ideal slew rates measuring in the kV/s range, while having clean, adjustable current limiting and low quiescent current consumption. Several common amplifier topologies are examined, with their merits and drawbacks discussed in the context of the use case. Ultimately, a hybridized approach is taken for an input stage for the amplifier that accomplishes high slew rates at the output while maintaining accurate, adjustable current limiting. The amplifier discussed, designed, and simulated operates at a 200 V rail-to-rail potential, with up to 1 A of continuous output current, with a slew rate exceeding 1 kV/s, drawing only 25 mA quiescent, and user-adjustable current limiting that operates without the need for an inefficient in-line current-sense resistor. The current limiting blocks discussed operate with a no excess DC current or power to operate apart from a small amount supplied for current-limiting adjustability.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>