2026-09-19T11:38:16Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1230742026-06-06T00:54:44Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Saman P. Amarasinghe.
Akkas, Abdurrahman.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2019-11-22T00:10:05Z
2019-11-22T00:10:05Z
2019
2019
https://hdl.handle.net/1721.1/123074
1127388618
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 59-60).
The increasing complexity of computer architectures with different memory hierarchies and parallelism characteristics makes generating efficient code a difficult task. Achieving high performance requires complex schedules and data layout transformations which might not be easy to express in a low level language. TIRAMISU [3] is an optimization framework for generating efficient code for different platforms including CPU, GPU, and distributed systems. It combines the polyhedral intermediate representation with rich scheduling and data layout commands, creating a high level interface to generate high performance code. In this thesis, we present new memory interfaces and GPU operators implemented to extend TIRAMISU compiler. We demonstrate that these features enable users to generate high performance GPU code with concise TIRAMISU programs. We also evaluate TIRAMISU's GPU backend with two benchmarks, matrix multiplication and a recurrent neural network architecture, showing that TIRAMISU outperforms other polyhedral compilers and popular library implementations.
by Abdurrahman Akkas.
M.Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
60 pages
eng
Massachusetts Institute of Technology
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Efficient memory and GPU operations for Tiramisu compiler
Efficient memory and graphics processing unit operations for Tiramisu compiler
Thesis
application/pdf
2020-03-09T19:58:07Z
Publication
unknown
unknown
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<Abstract>The increasing complexity of computer architectures with different memory hierarchies and parallelism characteristics makes generating efficient code a difficult task. Achieving high performance requires complex schedules and data layout transformations which might not be easy to express in a low level language. TIRAMISU [3] is an optimization framework for generating efficient code for different platforms including CPU, GPU, and distributed systems. It combines the polyhedral intermediate representation with rich scheduling and data layout commands, creating a high level interface to generate high performance code. In this thesis, we present new memory interfaces and GPU operators implemented to extend TIRAMISU compiler. We demonstrate that these features enable users to generate high performance GPU code with concise TIRAMISU programs. We also evaluate TIRAMISU's GPU backend with two benchmarks, matrix multiplication and a recurrent neural network architecture, showing that TIRAMISU outperforms other polyhedral compilers and popular library implementations.</Abstract>
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