2026-09-19T02:41:52Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1242472026-06-06T00:54:30Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Song Han.
Hafdi, Driss.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2020-03-24T15:36:16Z
2020-03-24T15:36:16Z
2019
2019
https://hdl.handle.net/1721.1/124247
1145118397
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 89-91).
Model quantization provides considerable latency and energy consumption reductions while preserving accuracy. However, the optimal bitwidth reduction varies on a layer by layer basis. This thesis suggests a novel neural network accelerator architecture that handles multiple bit precisions for both weights and activations. The architecture is based on a fused spatial and temporal micro-architecture that maximizes both bandwidth eciency and computational ability. Furthermore, this thesis presents an FPGA implementation of this new mixed precision architecture and it discusses the ISA and its associated bitcode compiler. Finally, the performance of the system is evaluated on a Virtex-9 UltraScale FPGA by running state-of-the-art neural networks.
by Driss Hafdi.
M.Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
91 pages
eng
Massachusetts Institute of Technology
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Mixed-precision architecture for flexible neural network accelerators
Thesis
application/pdf
2020-03-24T15:36:12Z
Publication
Master
EECS
unknown
unknown
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