2026-09-19T22:17:43Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1283432021-07-05T14:03:20Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anantha P. Chandrakasan and Hae-Seung Lee.
Mittal, Rishabh.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2020-11-03T20:31:58Z
2020-11-03T20:31:58Z
2020
2020
https://hdl.handle.net/1721.1/128343
1201912645
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 43-45).
A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock jitter to the forefront. Any jitter in the sampling clock edge adds a random error to the input signal thereby limiting the maximum achievable signal-to-noise ratio (SNR), and hence the effective resolution of the ADC. The effect of sampling clock jitter has been considered fundamental. In the proposed ADC, we do not sample the input upfront. Rather, we sample the residue from the first stage. Since the residue is bandlimited and has a small magnitude, therefore it will have a smaller derivative. Hence, the sensitivity to the clock jitter will be greatly reduced.
by Rishabh Mittal.
S.M.
S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
45 pages
eng
Massachusetts Institute of Technology
MIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A sampling jitter tolerant continuous-time pipeline ADC
Thesis
application/pdf
2020-11-03T20:31:57Z
Publication
Master
EECS
unknown
unknown
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<Abstract>A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock jitter to the forefront. Any jitter in the sampling clock edge adds a random error to the input signal thereby limiting the maximum achievable signal-to-noise ratio (SNR), and hence the effective resolution of the ADC. The effect of sampling clock jitter has been considered fundamental. In the proposed ADC, we do not sample the input upfront. Rather, we sample the residue from the first stage. Since the residue is bandlimited and has a small magnitude, therefore it will have a smaller derivative. Hence, the sensitivity to the clock jitter will be greatly reduced.</Abstract>
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