<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T09:08:14Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/129860" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/129860</identifier><datestamp>2026-06-06T00:55:08Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131023</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Jacob White and Taylor Hogan.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Zumbo, Zachary J.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department" lang="en_US">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2021-02-19T20:25:04Z</dim:field>
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   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2020</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2020</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">https://hdl.handle.net/1721.1/129860</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">1237567722</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Cataloged from student-submitted PDF of thesis.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (page 28).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">To meet increased demand and higher PCB design expectations, research engineers have been tasked to develop models to automate PCB placement and routing procedures using machine learning and artificial intelligence techniques. Since placement and routing are still tedious manual processes which limit the design search space, these techniques allow engineers to quickly investigate better solutions. The Move37 team within Cadence Design Systems found via placement to be a crucial problem to be solved and integrated into their OrbitIO platform. We evaluated multiple non-gradient-based optimization strategies and compiled data of their performance. From these tests, a genetic algorithm-based strategy was sought due to its fast convergence and the ability to substitute cost functions. In this study, we converted the via placement problem to a simpler layer assignment problem by enforcing the location of vias and pins to be the same. We then determined an optimal layer assignment given a set of flylines, i.e. logical connections, using a genetic optimization library called DEAP. We coined this genetic optimization approach to via strategy GO VIA.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Zachary J. Zumbo.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">M.Eng.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="collection" lang="en_US">M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">29 pages</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso" lang="en_US">eng</dim:field>
   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">MIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri" lang="en_US">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Genetic optimization applied to via and route strategy</dim:field>
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   	&lt;Title>Genetic optimization applied to via and route strategy&lt;/Title>
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   	&lt;PublicationDate>2020&lt;/PublicationDate>
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        	&lt;DisplayName>Zumbo, Zachary J.&lt;/DisplayName>
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    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>To meet increased demand and higher PCB design expectations, research engineers have been tasked to develop models to automate PCB placement and routing procedures using machine learning and artificial intelligence techniques. Since placement and routing are still tedious manual processes which limit the design search space, these techniques allow engineers to quickly investigate better solutions. The Move37 team within Cadence Design Systems found via placement to be a crucial problem to be solved and integrated into their OrbitIO platform. We evaluated multiple non-gradient-based optimization strategies and compiled data of their performance. From these tests, a genetic algorithm-based strategy was sought due to its fast convergence and the ability to substitute cost functions. In this study, we converted the via placement problem to a simpler layer assignment problem by enforcing the location of vias and pins to be the same. We then determined an optimal layer assignment given a set of flylines, i.e. logical connections, using a genetic optimization library called DEAP. We coined this genetic optimization approach to via strategy GO VIA.&lt;/Abstract>
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