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oai:dspace.mit.edu:1721.1/1390882026-01-05T12:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023

Arvind Huang, Tianhao(Data scientist) Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2022-01-14T14:49:13Z 2022-01-14T14:49:13Z 2021-06 2021-06-24T19:22:25.474Z https://hdl.handle.net/1721.1/139088 Graph pattern mining (GPM) is used in a variety of domains such as bioinformatics, e-commerce and social sciences. GPM is a computationally intensive problem with an enormous amount of coarse-grain parallelism and therefore, attractive for hardware acceleration. Unfortunately, existing GPM accelerators have not used the best known algorithms and optimizations, and thus offer questionable benefits over software implementations. We propose a software/hardware co-designed GPM accelerator that improves the efficiency without compromising the generality or productivity of state-of-the-art software GPM frameworks. It exploits the massive amount of coarse-grain parallelism in GPM with a large number of cheap, specialized processing elements. For efficient searches, the system adopts pattern-specific execution plans, which are generated automatically by a compiler from the given pattern(s). To avoid repetitive connectivity computation, an on-chip scratchpad is employed to memoize reusable intermediate results in the form of a connectivity map which enables fast vertex connectivity lookups. The proposed accelerator is implemented in a cycle-accurate simulator for performance evaluation. Key hardware modules are synthesized for an estimate of area costs. The results have shown that with similar core area as one modern CPU core, our design could outperform general-purpose systems by an order of magnitude. S.M. Massachusetts Institute of Technology In Copyright - Educational Use Permitted Copyright MIT http://rightsstatements.org/page/InC-EDU/1.0/ Designing a Domain-Specific Accelerator for Graph Pattern Mining Thesis application/pdf Master Master of Science in Electrical Engineering and Computer Science Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="53d800ee-9d17-4ba9-9ebf-52925803992b"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Title>Designing a Domain-Specific Accelerator for Graph Pattern Mining</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2021-06</PublicationDate> <Authors> <Author> <DisplayName>Huang, Tianhao(Data scientist)</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://rightsstatements.org/page/InC-EDU/1.0/</License> <Abstract>Graph pattern mining (GPM) is used in a variety of domains such as bioinformatics, e-commerce and social sciences. GPM is a computationally intensive problem with an enormous amount of coarse-grain parallelism and therefore, attractive for hardware acceleration. Unfortunately, existing GPM accelerators have not used the best known algorithms and optimizations, and thus offer questionable benefits over software implementations. We propose a software/hardware co-designed GPM accelerator that improves the efficiency without compromising the generality or productivity of state-of-the-art software GPM frameworks. It exploits the massive amount of coarse-grain parallelism in GPM with a large number of cheap, specialized processing elements. For efficient searches, the system adopts pattern-specific execution plans, which are generated automatically by a compiler from the given pattern(s). To avoid repetitive connectivity computation, an on-chip scratchpad is employed to memoize reusable intermediate results in the form of a connectivity map which enables fast vertex connectivity lookups. The proposed accelerator is implemented in a cycle-accurate simulator for performance evaluation. Key hardware modules are synthesized for an estimate of area costs. The results have shown that with similar core area as one modern CPU core, our design could outperform general-purpose systems by an order of magnitude.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>