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oai:dspace.mit.edu:1721.1/1393302022-01-15T03:14:48Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022

Chandrakasan, Anantha P. Banerjee, Utsav Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2022-01-14T15:04:29Z 2022-01-14T15:04:29Z 2021-06 2021-06-23T19:34:35.016Z https://hdl.handle.net/1721.1/139330 https://orcid.org/0000-0001-7949-4178 The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security a major concern. Security architectures for IoT devices, both software and hardware, must be low-power and have low energy consumption, while still providing strong cryptographic guarantees and side-channel resilience. Network security protocols use a variety of cryptographic algorithms to achieve these goals. However, the associated computational complexity makes it extremely important to have low-power and energy-efficient embedded implementations of cryptography, especially public key algorithms. The research presented in this thesis demonstrates the design, implementation and experimental validation of efficient next-generation cryptography for embedded systems using software optimization, hardware acceleration and software-hardware co-design, along with side-channel countermeasures. Using circuit, architecture and algorithm techniques, efficient hardware-accelerated implementations of elliptic curve cryptography, pairing-based cryptography, lattice-based cryptography and other post-quantum cryptography algorithms are demonstrated with up to two orders of magnitude energy savings compared to state-of-the-art software and hardware. These configurable hardware accelerators are further coupled with a low-power micro-processor to provide the flexibility to implement a wide variety of security protocols, thus enabling strong and affordable security for energy-limited IoT nodes. Ph.D. Massachusetts Institute of Technology In Copyright - Educational Use Permitted Copyright MIT http://rightsstatements.org/page/InC-EDU/1.0/ Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems Thesis application/pdf Doctoral Doctor of Philosophy Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="bfb89f8a-39a1-4860-a4dc-df27233e360a"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Title>Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2021-06</PublicationDate> <Authors> <Author> <DisplayName>Banerjee, Utsav</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://rightsstatements.org/page/InC-EDU/1.0/</License> <Abstract>The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security a major concern. Security architectures for IoT devices, both software and hardware, must be low-power and have low energy consumption, while still providing strong cryptographic guarantees and side-channel resilience. Network security protocols use a variety of cryptographic algorithms to achieve these goals. However, the associated computational complexity makes it extremely important to have low-power and energy-efficient embedded implementations of cryptography, especially public key algorithms. The research presented in this thesis demonstrates the design, implementation and experimental validation of efficient next-generation cryptography for embedded systems using software optimization, hardware acceleration and software-hardware co-design, along with side-channel countermeasures. Using circuit, architecture and algorithm techniques, efficient hardware-accelerated implementations of elliptic curve cryptography, pairing-based cryptography, lattice-based cryptography and other post-quantum cryptography algorithms are demonstrated with up to two orders of magnitude energy savings compared to state-of-the-art software and hardware. These configurable hardware accelerators are further coupled with a low-power micro-processor to provide the flexibility to implement a wide variety of security protocols, thus enabling strong and affordable security for energy-limited IoT nodes.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>