2026-09-18T23:41:58Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1400402022-02-08T03:33:15Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Amarasinghe, Saman
Chen, Yishen
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2022-02-07T15:20:29Z
2022-02-07T15:20:29Z
2021-09
2021-09-21T19:54:12.652Z
https://hdl.handle.net/1721.1/140040
Vector instructions are ubiquitous in modern processors. Traditional compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications in domains such as image processing, digital signal processing, and machine learning. To target non-SIMD instruction, compiler developers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. As vector instruction sets continue to rapidly evolve, compilers cannot keep up with these new hardware capabilities.
To facilitate the adaption of complex non-SIMD vector instructions, I propose a new model of vector parallelism that captures the semantics of these instructions and a new framework extracting this new model of vector parallelism automatically based on the formal semantics of the non-SIMD instructions.
S.M.
Massachusetts Institute of Technology
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http://rightsstatements.org/page/InC-EDU/1.0/
VeGen: A Vectorizer Generator for SIMD and Beyond
Thesis
application/pdf
Master
Master of Science in Electrical Engineering and Computer Science
Publication
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<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="8e423e8b-fc5e-4620-b2e9-e756f8aa6721">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Title>VeGen: A Vectorizer Generator for SIMD and Beyond</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2021-09</PublicationDate>
<Authors>
<Author>
<DisplayName>Chen, Yishen</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://rightsstatements.org/page/InC-EDU/1.0/</License>
<Abstract>Vector instructions are ubiquitous in modern processors. Traditional compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications in domains such as image processing, digital signal processing, and machine learning. To target non-SIMD instruction, compiler developers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. As vector instruction sets continue to rapidly evolve, compilers cannot keep up with these new hardware capabilities.
To facilitate the adaption of complex non-SIMD vector instructions, I propose a new model of vector parallelism that captures the semantics of these instructions and a new framework extracting this new model of vector parallelism automatically based on the formal semantics of the non-SIMD instructions.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>