2026-09-18T22:49:18Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1451512022-08-30T03:21:56Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Wachman, Silvina Hanono
Wang, Francis
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2022-08-29T16:36:38Z
2022-08-29T16:36:38Z
2022-05
2022-05-27T16:19:41.221Z
https://hdl.handle.net/1721.1/145151
This work introduces Verik, a hardware description language (HDL) for designing and verifying digital integrated circuits. Verik aims to be a drop-in replacement for SystemVerilog that leverages the productivity gains of the modern software stack to improve engineer productivity. Verik builds upon Kotlin, a modern general-purpose programming language with a clean and expressive syntax. Verik is Kotlin reinterpreted with the semantics of an HDL. The Verik toolchain consists of two parts, the compiler and the importer, and they serve to bridge the gap between the Kotlin and SystemVerilog environments. Verik is translated to SystemVerilog by the Verik compiler. This translation process is direct, typically with one-to-one correspondence between the input and output source files. Verik generates readable SystemVerilog output similar to what an engineer would have written. Conversely, SystemVerilog declarations can be imported into the Kotlin environment with the Verik importer. This allow us to make use of SystemVerilog libraries such as the Universal Verification Methodology (UVM) framework directly in Verik. We demonstrate Verik on a number of examples such as a RISC-V core and some UVM testbenches and show that it compares favorably against other popular HDLs used in academia and in industry. Finally, we recount the experience of using Verik with the Xilinx Vivado platform for a month-long FPGA workshop class.
M.Eng.
Massachusetts Institute of Technology
In Copyright - Educational Use Permitted
Copyright MIT
http://rightsstatements.org/page/InC-EDU/1.0/
Verik: Reinterpreting Kotlin as a Hardware Description Language
Thesis
application/pdf
Master
Master of Engineering in Electrical Engineering and Computer Science
Publication
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unknown
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<Abstract>This work introduces Verik, a hardware description language (HDL) for designing and verifying digital integrated circuits. Verik aims to be a drop-in replacement for SystemVerilog that leverages the productivity gains of the modern software stack to improve engineer productivity. Verik builds upon Kotlin, a modern general-purpose programming language with a clean and expressive syntax. Verik is Kotlin reinterpreted with the semantics of an HDL. The Verik toolchain consists of two parts, the compiler and the importer, and they serve to bridge the gap between the Kotlin and SystemVerilog environments. Verik is translated to SystemVerilog by the Verik compiler. This translation process is direct, typically with one-to-one correspondence between the input and output source files. Verik generates readable SystemVerilog output similar to what an engineer would have written. Conversely, SystemVerilog declarations can be imported into the Kotlin environment with the Verik importer. This allow us to make use of SystemVerilog libraries such as the Universal Verification Methodology (UVM) framework directly in Verik. We demonstrate Verik on a number of examples such as a RISC-V core and some UVM testbenches and show that it compares favorably against other popular HDLs used in academia and in industry. Finally, we recount the experience of using Verik with the Xilinx Vivado platform for a month-long FPGA workshop class.</Abstract>
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