2026-09-18T20:16:39Zhttps://dspace.mit.edu/server/oai/request

oai:dspace.mit.edu:1721.1/1515462023-08-01T04:16:46Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023

Yan, Mengjia Shay, Georgia Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2023-07-31T19:47:39Z 2023-07-31T19:47:39Z 2023-06 2023-06-06T16:35:38.333Z https://hdl.handle.net/1721.1/151546 Private information retrieval (PIR) is a protocol which allows a user to retrieve data from a database on a server without the server being able to deduce which records were retrieved. Due to the homomorphic cryptography systems required to make these protocols work and large amount of data processing required per user query, these algorithms tend to run much slower than needed for real-time applications such as streaming movies or voice calling. To improve these speeds to ones more tolerable for user applications, we designed OnionChopper: a small, fast, and energy efficient hardware accelerator on which to offload the heaviest computational work. This hardwareaccelerator is optimized for astate-of-the-art PIRalgorithm, Onion- PIR, but is widely applicable due to similarities in the fundamental algorithms and cryptographies used in private information retrieval. We identified the major bottle- neck operation common to OnionPIR and other PIR schemes and designed computation units to aid with that operation. We designed a near-storage accelerator with on-chip parallel computation units, SRAMs and register files for exploiting data reuse, and a near-storage connection to the SSD to exploit its high internal bandwidth to access the database. We used a space exploration tool to identify the optimal architecture and scheme of computation and data movement over that architecture. Our resulting design offers a nearly300×speed improvement over running on a general- purpose processor for a 64GB database. M.Eng. Massachusetts Institute of Technology In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ OnionChopper: A Modular Arithmetic Hardware Accelerator for Private Information Retrieval Thesis application/pdf Master Master of Engineering in Electrical Engineering and Computer Science Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="19fe710c-80e5-4cd2-b006-a2c7518a9ec9"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Title>OnionChopper: A Modular Arithmetic Hardware Accelerator for Private Information Retrieval</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2023-06</PublicationDate> <Authors> <Author> <DisplayName>Shay, Georgia</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>https://rightsstatements.org/page/InC-EDU/1.0/</License> <Abstract>Private information retrieval (PIR) is a protocol which allows a user to retrieve data from a database on a server without the server being able to deduce which records were retrieved. Due to the homomorphic cryptography systems required to make these protocols work and large amount of data processing required per user query, these algorithms tend to run much slower than needed for real-time applications such as streaming movies or voice calling. To improve these speeds to ones more tolerable for user applications, we designed OnionChopper: a small, fast, and energy efficient hardware accelerator on which to offload the heaviest computational work. This hardwareaccelerator is optimized for astate-of-the-art PIRalgorithm, Onion- PIR, but is widely applicable due to similarities in the fundamental algorithms and cryptographies used in private information retrieval. We identified the major bottle- neck operation common to OnionPIR and other PIR schemes and designed computation units to aid with that operation. We designed a near-storage accelerator with on-chip parallel computation units, SRAMs and register files for exploiting data reuse, and a near-storage connection to the SSD to exploit its high internal bandwidth to access the database. We used a space exploration tool to identify the optimal architecture and scheme of computation and data movement over that architecture. Our resulting design offers a nearly300×speed improvement over running on a general- purpose processor for a 64GB database.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>