2026-09-20T03:31:08Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1527052023-11-03T03:57:10Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Kirtley Jr., James L.
Lynch, William A.
Negm, Ahmad H.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2023-11-02T20:09:48Z
2023-11-02T20:09:48Z
2023-09
2023-10-03T18:21:06.186Z
https://hdl.handle.net/1721.1/152705
With the increased utilization of and reliance on battery-powered and -storage systems, battery cell voltage balancers are crucial in providing additional capacity extraction and lifespan from battery packs. This thesis explores the analysis, design, and evaluation of a hierarchical switched-capacitor cell voltage balancer topology that employs canonical charge pump inverters as fundamental building blocks. The charge pump inverter implementation was first designed using a fully N-channel switch configuration and a mixed N- and P-channel switch configuration. This was tested at the 2S, 4S, 8S, and 32S battery configuration voltage levels for combined cell stack voltages up to 100V. Subsequently, a complete 4S multi-level implementation of the hierarchical topology was designed around distinct N- and P-channel switch configurations at the 2S and 4S levels. The control circuitry ran off a single external dual-supply by implementing discrete charge pump circuits as floating supplies for the gate drivers. Testing on 2.5Ah capacity and 0mΩ inner resistance emulated cells with 0.4V imbalance yielded a typical balance time under 20 min. Although the topology scales moderately poorly with respect to component count and stress, it excelled at edge-to-edge cell balancing. Overall, the work in this thesis demonstrates the proposed hierarchical balancer topology from 10s of Amps to 33.56A peak cell balance current, 10s of Watts to 1.67kW output power, and typically >90% efficiency.
M.Eng.
Massachusetts Institute of Technology
In Copyright - Educational Use Permitted
Copyright retained by author(s)
https://rightsstatements.org/page/InC-EDU/1.0/
Analysis, Design, and Evaluation of Hierarchical Switched-Capacitor Cell Voltage Balancers
Thesis
application/pdf
Master
Master of Engineering in Electrical Engineering and Computer Science
Publication
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unknown
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<Abstract>With the increased utilization of and reliance on battery-powered and -storage systems, battery cell voltage balancers are crucial in providing additional capacity extraction and lifespan from battery packs. This thesis explores the analysis, design, and evaluation of a hierarchical switched-capacitor cell voltage balancer topology that employs canonical charge pump inverters as fundamental building blocks. The charge pump inverter implementation was first designed using a fully N-channel switch configuration and a mixed N- and P-channel switch configuration. This was tested at the 2S, 4S, 8S, and 32S battery configuration voltage levels for combined cell stack voltages up to 100V. Subsequently, a complete 4S multi-level implementation of the hierarchical topology was designed around distinct N- and P-channel switch configurations at the 2S and 4S levels. The control circuitry ran off a single external dual-supply by implementing discrete charge pump circuits as floating supplies for the gate drivers. Testing on 2.5Ah capacity and 0mΩ inner resistance emulated cells with 0.4V imbalance yielded a typical balance time under 20 min. Although the topology scales moderately poorly with respect to component count and stress, it excelled at edge-to-edge cell balancing. Overall, the work in this thesis demonstrates the proposed hierarchical balancer topology from 10s of Amps to 33.56A peak cell balance current, 10s of Watts to 1.67kW output power, and typically >90% efficiency.</Abstract>
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