2026-09-19T02:44:50Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1538592024-03-22T03:17:09Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Sze, Vivienne
Erner, Joel
Feldman, Andrew
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2024-03-21T19:11:10Z
2024-03-21T19:11:10Z
2024-02
2024-03-04T16:37:57.235Z
https://hdl.handle.net/1721.1/153859
Specialized microarchitectures for exploiting sparsity have been critical to the design of sparse tensor accelerators. Sparseloop introduced the Sparse Acceleration Feature (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations.
Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies required for implementing SAFs (referred to in this work as "SAF microarchitectures".)
Analysis of prior works shows that SAF microarchitectures may or may not constitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads.
Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a conceptual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a component library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation.
M.Eng.
Massachusetts Institute of Technology
In Copyright - Educational Use Permitted
Copyright retained by author(s)
https://rightsstatements.org/page/InC-EDU/1.0/
Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators
Thesis
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Master
Master of Engineering in Electrical Engineering and Computer Science
Publication
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<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="c1fc74b9-08f1-4b3a-89bd-e701c9968158">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Title>Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2024-02</PublicationDate>
<Authors>
<Author>
<DisplayName>Feldman, Andrew</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>https://rightsstatements.org/page/InC-EDU/1.0/</License>
<Abstract>Specialized microarchitectures for exploiting sparsity have been critical to the design of sparse tensor accelerators. Sparseloop introduced the Sparse Acceleration Feature (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations.
Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies required for implementing SAFs (referred to in this work as "SAF microarchitectures".)
Analysis of prior works shows that SAF microarchitectures may or may not constitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads.
Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a conceptual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a component library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>