<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T13:48:36Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/153863" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/153863</identifier><datestamp>2024-03-25T14:33:27Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131022</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor">Palacios, Tomás</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author">Xie, Qingyun</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2024-03-21T19:11:29Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2024-03-21T19:11:29Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued">2024-02</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="submitted">2024-02-21T17:19:15.651Z</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">https://hdl.handle.net/1721.1/153863</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract">Gallium nitride (GaN) integrated circuits (ICs) are receiving increasing attention because they offer compactness, reduced parasitics, and higher performance compared to discrete transistors or printed circuit board (PCB) integration. The p-GaN platform exhibits tremendous potential in power ICs and recently, in high temperature (500 °C) digital circuits. While the initial demonstrations offer promising results, several challenges remain. Notably, the lack of a monolithically integrated GaN complementary technology impedes the advancement of GaN power ICs.&#xd;
&#xd;
This thesis aims to enhance the p-GaN platform (GaN-CMOS platform) (CMOS: complementary metal-oxide-semiconductor) through developing the next generation of GaN complementary technology (p-channel and n-channel field-effect transistors (FETs)). Based on the GaN-CMOS platform, the aggressive scaling of novel complementary transistors (self-aligned-gate p-FET and self-aligned metal/p-GaN-gate HEMT) is pursued. Alternative metallization schemes and a new technology for gate recess in GaN p-FETs are demonstrated. The unique characteristics of the p-FET are revealed through a combination of experimental measurements and TCAD simulations. The p-FET (based on GaN-CMOS platform) and p-GaN-gate n-FETs are analyzed for high temperature operation. Lastly, in order to aid the future design of more complex circuits based on the p-GaN platform, a device-to-circuit CAD framework was developed for GaN n-FET circuits and validated at high temperature up to 500 °C.&#xd;
&#xd;
To the best of the author’s knowledge, the above results represent the state-of-the-art in GaN complementary technology and GaN electronics based on the p-GaN platform. These findings are expected to deliver wider impact in the areas of power, RF/mixed-signal, and high temperature electronics.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree">Ph.D.</dim:field>
   <dim:field mdschema="dc" element="publisher">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights">In Copyright - Educational Use Permitted</dim:field>
   <dim:field mdschema="dc" element="rights">Copyright retained by author(s)</dim:field>
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   <dim:field mdschema="dc" element="title">p-GaN Platform for Next-Generation GaN Complementary Transistors and Circuits</dim:field>
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   <dim:field mdschema="mit" element="thesis" qualifier="degree">Doctoral</dim:field>
   <dim:field mdschema="thesis" element="degree" qualifier="name">Doctor of Philosophy</dim:field>
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   	&lt;Title>p-GaN Platform for Next-Generation GaN Complementary Transistors and Circuits&lt;/Title>
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   	&lt;PublicationDate>2024-02&lt;/PublicationDate>
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        	&lt;DisplayName>Xie, Qingyun&lt;/DisplayName>
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            &lt;DisplayName>Massachusetts Institute of Technology&lt;/DisplayName>
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   	&lt;Abstract>Gallium nitride (GaN) integrated circuits (ICs) are receiving increasing attention because they offer compactness, reduced parasitics, and higher performance compared to discrete transistors or printed circuit board (PCB) integration. The p-GaN platform exhibits tremendous potential in power ICs and recently, in high temperature (500 °C) digital circuits. While the initial demonstrations offer promising results, several challenges remain. Notably, the lack of a monolithically integrated GaN complementary technology impedes the advancement of GaN power ICs.&#xd;
&#xd;
This thesis aims to enhance the p-GaN platform (GaN-CMOS platform) (CMOS: complementary metal-oxide-semiconductor) through developing the next generation of GaN complementary technology (p-channel and n-channel field-effect transistors (FETs)). Based on the GaN-CMOS platform, the aggressive scaling of novel complementary transistors (self-aligned-gate p-FET and self-aligned metal/p-GaN-gate HEMT) is pursued. Alternative metallization schemes and a new technology for gate recess in GaN p-FETs are demonstrated. The unique characteristics of the p-FET are revealed through a combination of experimental measurements and TCAD simulations. The p-FET (based on GaN-CMOS platform) and p-GaN-gate n-FETs are analyzed for high temperature operation. Lastly, in order to aid the future design of more complex circuits based on the p-GaN platform, a device-to-circuit CAD framework was developed for GaN n-FET circuits and validated at high temperature up to 500 °C.&#xd;
&#xd;
To the best of the author’s knowledge, the above results represent the state-of-the-art in GaN complementary technology and GaN electronics based on the p-GaN platform. These findings are expected to deliver wider impact in the areas of power, RF/mixed-signal, and high temperature electronics.&lt;/Abstract>
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