2026-09-18T21:47:17Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1562732024-08-22T03:59:53Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Chlipala, Adam
Arvind
Liu, Jiazheng
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2024-08-21T18:53:03Z
2024-08-21T18:53:03Z
2024-05
2024-07-10T12:59:44.755Z
https://hdl.handle.net/1721.1/156273
Programmable network switches are complex pieces of hardware that leverage nonobvious optimizations such as pipelining to offer flexible configuration interfaces. In this thesis, we propose a novel formal-verification methodology aimed at establishing strong correctness theorems for synthesizable hardware designs for network functionality, demonstrated through a case-study analysis of a Tofino-like programmable switch that we call VeriSwit. Our approach hinges on modularity, whereby the system is split into interconnected units, each equipped with its specification and proof, oblivious to the internals of other units. We conduct VeriSwit’s modular verification in the Coq theorem prover. Experiments with synthesis for both FPGA and ASIC targets, combined with simulation, show that 100 GB/s line rate is easily achieved.
S.M.
Massachusetts Institute of Technology
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https://rightsstatements.org/page/InC-EDU/1.0/
Formally Verifying a Programmable Network Switch
Thesis
application/pdf
Master
Master of Science in Electrical Engineering and Computer Science
Publication
unknown
unknown
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<Abstract>Programmable network switches are complex pieces of hardware that leverage nonobvious optimizations such as pipelining to offer flexible configuration interfaces. In this thesis, we propose a novel formal-verification methodology aimed at establishing strong correctness theorems for synthesizable hardware designs for network functionality, demonstrated through a case-study analysis of a Tofino-like programmable switch that we call VeriSwit. Our approach hinges on modularity, whereby the system is split into interconnected units, each equipped with its specification and proof, oblivious to the internals of other units. We conduct VeriSwit’s modular verification in the Coq theorem prover. Experiments with synthesis for both FPGA and ASIC targets, combined with simulation, show that 100 GB/s line rate is easily achieved.</Abstract>
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