2026-09-19T11:37:04Zhttps://dspace.mit.edu/server/oai/request

oai:dspace.mit.edu:1721.1/1562862024-08-22T03:11:11Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023

del Alamo, Jesús A. Shen, Dingyu Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2024-08-21T18:54:04Z 2024-08-21T18:54:04Z 2024-05 2024-07-10T12:59:57.229Z https://hdl.handle.net/1721.1/156286 https://orcid.org/0009-0004-9904-8318 Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses. S.M. Massachusetts Institute of Technology In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ Device Stack Optimization for Protonic Non-Volatile Programmable Resistors Thesis application/pdf Master Master of Science in Electrical Engineering and Computer Science Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="cb669f50-ea4f-4862-9274-afca9a12c866"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Title>Device Stack Optimization for Protonic Non-Volatile Programmable Resistors</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2024-05</PublicationDate> <Authors> <Author> <DisplayName>Shen, Dingyu</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>https://rightsstatements.org/page/InC-EDU/1.0/</License> <Abstract>Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>