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Sze, Vivienne Wojtyna, Adrianna D. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2024-09-24T18:25:44Z 2024-09-24T18:25:44Z 2024-05 2024-07-11T14:37:32.844Z https://hdl.handle.net/1721.1/156997 Micro-robots play an important role in numerous tasks, including search and rescue, exploration, and navigation. A significant challenge to their deployment is their limited energy capacity, which constrains the computation such systems can complete. Specifically, 3D mapping algorithms significantly contribute to the compute power footprint as a result of repeated memory accesses. A promising approach involving Gaussian Mixture Models (GMMs), Single-Pass Gaussian Fitting (SPGF) algorithm, allowed for real-time 3D mapping with minimal memory and energy requirements due to its single-pass processing of input data. To further decrease demonstrated energy results, we propose the design of an FPGA (Field Programmable Gate Array)-based hardware accelerator that enables Gaussian fitting based on the SPGF algorithm with 10.4× lower energy per image (based on post-implementation power analysis), compared to the original, software implementation. By using fixed-point numerical representation and concurrent processing of data inputs, our proposed hardware accelerator, when operating at 100MHz, is capable of processing depth images at an average rate of 303.09 frames per second (fps), allowing for 7.97× improvement compared to the original software implementation of SPGF (32fps). We also demonstrated 46.1× lower average FPGA resource utilization compared to the previously proposed hardware accelerator for GMMs. Our proposed design was demonstrated as part of the complete subsystem, allowing for visualization of the constructed map in real-time. The proposed design was demonstrated to perform at 100MHz in isolation and verified for its performance with a 50MHz subsystem on AMD Virtex UltraScale+ VCU118 FPGA. M.Eng. Massachusetts Institute of Technology Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) Copyright retained by author(s) https://creativecommons.org/licenses/by-nc-nd/4.0/ Energy-Efficient Real-Time Hardware Acceleration for Gaussian Fitting Thesis application/pdf Master Master of Engineering in Electrical Engineering and Computer Science Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="cd20736e-daae-409b-829f-ce93440f7ac6"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Title>Energy-Efficient Real-Time Hardware Acceleration for Gaussian Fitting</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2024-05</PublicationDate> <Authors> <Author> <DisplayName>Wojtyna, Adrianna D.</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>https://creativecommons.org/licenses/by-nc-nd/4.0/</License> <Abstract>Micro-robots play an important role in numerous tasks, including search and rescue, exploration, and navigation. A significant challenge to their deployment is their limited energy capacity, which constrains the computation such systems can complete. Specifically, 3D mapping algorithms significantly contribute to the compute power footprint as a result of repeated memory accesses. A promising approach involving Gaussian Mixture Models (GMMs), Single-Pass Gaussian Fitting (SPGF) algorithm, allowed for real-time 3D mapping with minimal memory and energy requirements due to its single-pass processing of input data. To further decrease demonstrated energy results, we propose the design of an FPGA (Field Programmable Gate Array)-based hardware accelerator that enables Gaussian fitting based on the SPGF algorithm with 10.4× lower energy per image (based on post-implementation power analysis), compared to the original, software implementation. By using fixed-point numerical representation and concurrent processing of data inputs, our proposed hardware accelerator, when operating at 100MHz, is capable of processing depth images at an average rate of 303.09 frames per second (fps), allowing for 7.97× improvement compared to the original software implementation of SPGF (32fps). We also demonstrated 46.1× lower average FPGA resource utilization compared to the previously proposed hardware accelerator for GMMs. Our proposed design was demonstrated as part of the complete subsystem, allowing for visualization of the constructed map in real-time. The proposed design was demonstrated to perform at 100MHz in isolation and verified for its performance with a 50MHz subsystem on AMD Virtex UltraScale+ VCU118 FPGA.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>