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oai:dspace.mit.edu:1721.1/1627132025-09-19T04:49:28Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023

Reiskarimian, Negar Guobadia, Omozusi E. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2025-09-18T14:28:39Z 2025-09-18T14:28:39Z 2025-05 2025-06-23T14:02:03.275Z https://hdl.handle.net/1721.1/162713 The advancement of brain-machine interfaces (BMIs) requires neural signal acquisition systems that are capable of resolving both fast, low-amplitude action potentials (APs) and slow, higher-amplitude local field potentials (LFPs) under stringent power and area constraints. This thesis presents the design and simulation of a high-resolution, low-power successive approximation register (SAR) analog-to-digital converter (ADC) tailored for sub-cortical neural signal detection. To optimize dynamic range and reduce power consumption, a novel adaptive zoom-and-tracking architecture is introduced, enabling the ADC to dynamically adjust its reference window based on LFP trends while maintaining high-resolution capture of APs. The proposed system integrates a bootstrapped track-and-hold circuit, a differential capacitive DAC, and a strong-arm comparator in the analog front-end, alongside a digital FIR filter and SAR logic with zoom-range control in the digital domain. Simulations validate the functionality of each subsystem independently and in concert, demonstrating the system’s ability to dynamically isolate APs from LFP-dominated baselines while reducing analog power draw by over 60% compared to fixed-range ADCs. This work offers a promising approach for scalable, energy-efficient neural recording architectures suited to future BMI applications. M.Eng. Massachusetts Institute of Technology In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ Design of High-Resolution SAR ADC for Detection of Sub-Cortical Neuron Action Potentials for BMI Applications Thesis application/pdf Master Master of Engineering in Electrical Engineering and Computer Science Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="f791b689-8226-45d3-ba13-4b4b428f1023"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Title>Design of High-Resolution SAR ADC for Detection of Sub-Cortical Neuron Action Potentials for BMI Applications</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2025-05</PublicationDate> <Authors> <Author> <DisplayName>Guobadia, Omozusi E.</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>https://rightsstatements.org/page/InC-EDU/1.0/</License> <Abstract>The advancement of brain-machine interfaces (BMIs) requires neural signal acquisition systems that are capable of resolving both fast, low-amplitude action potentials (APs) and slow, higher-amplitude local field potentials (LFPs) under stringent power and area constraints. This thesis presents the design and simulation of a high-resolution, low-power successive approximation register (SAR) analog-to-digital converter (ADC) tailored for sub-cortical neural signal detection. To optimize dynamic range and reduce power consumption, a novel adaptive zoom-and-tracking architecture is introduced, enabling the ADC to dynamically adjust its reference window based on LFP trends while maintaining high-resolution capture of APs. The proposed system integrates a bootstrapped track-and-hold circuit, a differential capacitive DAC, and a strong-arm comparator in the analog front-end, alongside a digital FIR filter and SAR logic with zoom-range control in the digital domain. Simulations validate the functionality of each subsystem independently and in concert, demonstrating the system’s ability to dynamically isolate APs from LFP-dominated baselines while reducing analog power draw by over 60% compared to fixed-range ADCs. This work offers a promising approach for scalable, energy-efficient neural recording architectures suited to future BMI applications.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>