2026-09-21T15:04:22Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/1646422026-01-30T03:24:44Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
O’Brien, Kevin P.
Kline, Jeremy B.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2026-01-29T15:05:21Z
2026-01-29T15:05:21Z
2025-09
2025-09-15T14:41:12.012Z
https://hdl.handle.net/1721.1/164642
Currently, superconducting qubit processors are bottlenecked by errors during two-qubit gates, readout, and idle time. All three error contributions could be reduced if we improved the speed of operations (without introducing additional leakage errors) compared to the qubit lifetime. Readout and two-qubit gates are multimode interactions and therefore are limited by the coupling strength between the modes. In this thesis, we introduce a two-mode superconducting qubit which uses one mode to facilitate strong coupling to other modes of the quantum processor and one mode to store data with high coherence. Simulations show that this architecture could enable order-of-magnitude reductions in error during readout and two-qubit gates.
S.M.
Massachusetts Institute of Technology
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https://rightsstatements.org/page/InC-EDU/1.0/
The Arm Qubit for Faster, Higher Fidelity Readout and Gates
Thesis
application/pdf
Master
Master of Science in Electrical Engineering and Computer Science
Publication
unknown
unknown
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<Abstract>Currently, superconducting qubit processors are bottlenecked by errors during two-qubit gates, readout, and idle time. All three error contributions could be reduced if we improved the speed of operations (without introducing additional leakage errors) compared to the qubit lifetime. Readout and two-qubit gates are multimode interactions and therefore are limited by the coupling strength between the modes. In this thesis, we introduce a two-mode superconducting qubit which uses one mode to facilitate strong coupling to other modes of the quantum processor and one mode to store data with high coherence. Simulations show that this architecture could enable order-of-magnitude reductions in error during readout and two-qubit gates.</Abstract>
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