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John F. McKenna and Thomas F. Knight. Woods-Corwin, Robert, 1978- Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2005-05-19T14:33:21Z 2005-05-19T14:33:21Z 2001 2001 http://hdl.handle.net/1721.1/16777 49322896 Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. Includes bibliographical references (p. 89-91). This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. This thesis describes the design and synthesis of an updated routing block for a nextgeneration wave propagation limited fault-tolerant interconnect fabric for a large-scale shared-memory multiprocessor system. The design is based on the metro multistage interconnection network, and is targeted at minimizing message latency. The design incorporates an efficient new tree-based allocation mechanism and an idempotent messaging protocol. A fat tree topology is the basis for the network. A Verilog implementation of the design is simulated and synthesized into physical hardware, running at speeds as high as 90MHz in an FPGA. Techniques are discussed to vastly improve performance in a potential future design using custom hardware. Further, two potential modifications to the network are considered. First, the performance effect of allocating dedicated physical wires to streamline the idempotent messaging protocol is analyzed. The modification increases the success rate of messages significantly, but the increased latency due to the space taken by the wires overwhelms the potential performance advantage. Second, a scheme for prioritizing messages is developed. This scheme improves the message success rates almost as much as the first modification, reducing the latency of idempotent messages by over 10%. However, this scheme does not increase the number of wires, and has a much smaller overhead. In addition to providing a significant performance advantage, prioritizing messages can help avoid deadlock and livelock situations. by Robert Woods-Corwin. M.Eng. 91 p. 373708 bytes 373342 bytes application/pdf application/pdf eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. A high-speed fault-tolerant interconnect fabric for large-scale multiprocessors Thesis application/pdf Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="e602a71a-7452-4500-910f-b929fa50b7be"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>A high-speed fault-tolerant interconnect fabric for large-scale multiprocessors</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2001</PublicationDate> <Authors> <Author> <DisplayName>Woods-Corwin, Robert, 1978-</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>This thesis describes the design and synthesis of an updated routing block for a nextgeneration wave propagation limited fault-tolerant interconnect fabric for a large-scale shared-memory multiprocessor system. The design is based on the metro multistage interconnection network, and is targeted at minimizing message latency. The design incorporates an efficient new tree-based allocation mechanism and an idempotent messaging protocol. A fat tree topology is the basis for the network. A Verilog implementation of the design is simulated and synthesized into physical hardware, running at speeds as high as 90MHz in an FPGA. Techniques are discussed to vastly improve performance in a potential future design using custom hardware. Further, two potential modifications to the network are considered. First, the performance effect of allocating dedicated physical wires to streamline the idempotent messaging protocol is analyzed. The modification increases the success rate of messages significantly, but the increased latency due to the space taken by the wires overwhelms the potential performance advantage. Second, a scheme for prioritizing messages is developed. This scheme improves the message success rates almost as much as the first modification, reducing the latency of idempotent messages by over 10%. However, this scheme does not increase the number of wires, and has a much smaller overhead. In addition to providing a significant performance advantage, prioritizing messages can help avoid deadlock and livelock situations.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>