2026-09-19T06:14:35Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/168552022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Michael Fu and Jacob K. White.
Paskalev, Krassimir (Krassimir Ivanov), 1978-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-05-19T15:02:20Z
2005-05-19T15:02:20Z
2002
2002
http://hdl.handle.net/1721.1/16855
51588096
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (leaves 28-29).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
A new model for the propagation delay between two logic gates for timing-driven global placement is proposed. The model is a function of the number of pins on the net, the half perimeter of the bounding box enclosing the net, and the half perimeter of the bounding box enclosing the driving pin and the sink pin. On a training set of two designs and testing set of another two, the proposed model is 31% more accurate than the current state-of-the-art model and has comparable computational complexity.
by Krassimir Paskalev.
M.Eng.
29 leaves
475019 bytes
474775 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Wire delay models for global placement of ASICs
Wire delay models for global placement of Application-Specific Integrated Circuits
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