2026-09-19T07:42:37Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/168592022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Richard E. Anderson and Anantha P. Chandrakasan.
Shah, Rajul R. (Rajul Ramesh), 1979-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-05-19T15:03:10Z
2005-05-19T15:03:10Z
2002
2002
http://hdl.handle.net/1721.1/16859
51619520
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (p. 143-144).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
In this project, a JPEG compliant, low-power dedicated, two-dimensional, Discrete Cosine Transform (DCT) core meeting all IBM Softcore requirements is developed. Power is optimized completely at the algorithmic, architectural, and logic levels. The architecture uses row-column decomposition of a fast 1-D algorithm implemented with distributed arithmetic. It features clock gating schemes as well as power-aware schemes that utilize input correlations to dynamically scale down power consumption. This is done by eliminating glitching in the ROM Accumulate (RAC) units to effectively stop unnecessary computation. The core is approximately 180K transistors, runs at a maximum of 100MHz, is synthesized to a .18[mu]m double-well CMOS technology with a 1.8V power supply, and consumes between 63 and 87 mW of power at 100MHz depending on the image data. The thesis explores the algorithmic evaluations, architectural design, development of the C and VHDL models, verification methods, synthesis operations, static timing analysis, design for test compliance, power analysis, and performance comparisons for the development of the core. The work has been completed in the ASIC Digital Cores I department of the IBM Microelectronics Division in Burlington, Vermont as part of the third assignment in the MIT VI-A program.
by Rajul R. Shah.
M.Eng.
144 p.
629721 bytes
629478 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Hardware implementation of a low-power two-dimensional discrete cosine transform
Thesis
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