2026-09-19T00:45:35Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/169672026-06-06T01:04:36Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Michael H. Perrott.
Ginsburg, Brian P. (Brian Paul), 1980-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-05-19T15:28:46Z
2005-05-19T15:28:46Z
2003
2003
http://hdl.handle.net/1721.1/16967
53472199
Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 119-124).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Most PLL research focuses on narrowband systems that support only one communication standard. For a flexible system, it may be desirable to support multiple standards. A single PLL capable of operating over a wide frequency range while meeting all the requirements of the individual standards can save area and design effort, compared with multiple PLLs each supporting only one standard. This thesis presents a PLL that has a very wide tuning range, accurate quadrature outputs, and is geared towards low phase noise. The VCO is identified as the limiting factor in the tuning range and source of the quadrature outputs, as well as the primary source of the phase noise above the loop bandwidth of the PLL, so its design is the principle focus herein. The VCO uses digitally switched capacitors to extend the tuning range. It consists of two cross-coupled cores that produce quadrature outputs, where phase error arises if the cores are not identical. The VCO's output also has a controlled amplitude and common mode point. The charge pump of the PLL is designed to compensate for variations in the VCO's gain at different frequencies. In simulations using a 0.13 [mu]m CMOS process, the VCO achieves a tuning range of 1.585-3.254GHz over process and temperature variations. Its quadrature outputs have less than 2.6° phase error for a 2% mismatch in the capacitance between the two LC-tanks. The phase noise, calculated assuming a linear, time-variant model, is -109.5dBc/Hz at 600kHz offset from 3.217GHz.
by Brian P. Ginsburg.
M.Eng.
S.B.
124 p.
1446536 bytes
1446463 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A 1.6-3.2GHz, high phase accuracy quadrature phase locked loop
1.6-3.2 GigaHertz, high phase accuracy quadrature PLL
Thesis
application/pdf
Publication
unknown
unknown
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