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   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Christopher J. Terman.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Oey, James Boe-Kian, 1980-</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2005-06-02T19:41:55Z</dim:field>
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   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2003</dim:field>
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   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">57241123</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (p. 161).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by James Boe-Kian Oey.</dim:field>
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   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.</dim:field>
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   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Cell-based array for deep sub-micron technologies</dim:field>
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   	&lt;Title>Cell-based array for deep sub-micron technologies&lt;/Title>
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   	&lt;Abstract>In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.&lt;/Abstract>
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