2026-09-19T10:12:29Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/180342022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Rohit Kapur and Daniel A. Spielman.
Sitchinava, Nodari S. (Nodari Shalva), 1981-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-06-02T19:42:50Z
2005-06-02T19:42:50Z
2003
2003
http://hdl.handle.net/1721.1/18034
57253435
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 61-64).
Fast developments in semiconductor industry have led to smaller and cheaper integrated circuit (IC) components. As the designs become larger and more complex, larger amount of test data is required to test them. This results in longer test application times, therefore, increasing cost of testing each chip. This thesis describes an architecture, named Dynamic Scan, that allows to reduce this cost by reducing the test data volume and, consequently, test application time. The Dynamic Scan architecture partitions the scan chains of the IC design into several segments by a set of multiplexers. The multiplexers allow bypassing or including a particular segment during the test application on the automatic test equipment. The optimality criteria for partitioning scan chains into segments, as well as a partitioning algorithm based on this criteria are also introduced. According to our experimental results Dynamic Scan provides almost a factor of five reduction in test data volume and test application time. More theoretical results reach as much as ten times the reductions compared to the classical scan methodologies.
by Nodari S. Sitchinava.
M.Eng.
64 p.
2707604 bytes
2713809 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Dynamic scan chains : a novel architecture to lower the cost of VLSI test
Thesis
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