<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T13:12:01Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/26889" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/26889</identifier><datestamp>2022-01-13T07:54:29Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131022</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Srinivas Devadas.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Chatterjee, Sandeep, 1973-</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2005-09-06T20:40:35Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2005-09-06T20:40:35Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2001</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2001</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">http://hdl.handle.net/1721.1/26889</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">48971823</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (p. 169-173).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">(cont.) In this thesis, I describe an architecture for network devices that is based on using pluggable system resource modules that can be composed together to create a close-to-optimal platform for a particular application mix and device. Frequently used applications execute efficiently, while infrequently used applications execute less efficiently. Metrics for calculating efficiencies and selected application domains and mixes are specified by individuals as opposed to one-size-fits- all metrics specified by manufacturers. I show that such a composable system architecture is effective in optimizing system performance with respect to user preferences and application requirements, while the modularity of the architecture introduces little overhead. I also explore opportunities that arise from segmenting devices into UI and computational resource components, and show that an automated design environment can be created that greatly simplifies custom device design, reducing time-to-market and lowering costs.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">Network devices promise to provide a variety of user interfaces through which users can interact with network applications. The design of these devices stand in stark contrast to the design of personal computers in which new software content is accommodated by increased processor performance. Network device design, on the other hand, must take into consideration a variety of metrics including interactive performance, power consumption, battery life, transaction security, physical size and weight, and cost. Designing a general-purpose platform that caters to all of these metrics for all applications and devices is impractical. For an application mix, a processor architecture and platform can be designed that is optimized for a selected set of metrics, such as power consumption and battery life. Each of these optimized processor architectures and platforms will no doubt be applicable to a variety of devices. This suggests a modular system architecture for network devices that segments the computational resources from the device UI. Computational resources can be selected for a device UI that are optimized with respect to application mixes as well as to user preferences and metrics. Segmenting out the device UI reduces the complexity of device UIs, simplifying development and lowering costs. At the same time, with little electrical circuitry resident on device UIs, the selected platform can more fully optimize the entire device.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Sandeep Chatterjee.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">Ph.D.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">173 p.</dim:field>
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   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Composable system resources as an architecture for networked systems</dim:field>
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   	&lt;Title>Composable system resources as an architecture for networked systems&lt;/Title>
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   	&lt;PublicationDate>2001&lt;/PublicationDate>
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    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>(cont.) In this thesis, I describe an architecture for network devices that is based on using pluggable system resource modules that can be composed together to create a close-to-optimal platform for a particular application mix and device. Frequently used applications execute efficiently, while infrequently used applications execute less efficiently. Metrics for calculating efficiencies and selected application domains and mixes are specified by individuals as opposed to one-size-fits- all metrics specified by manufacturers. I show that such a composable system architecture is effective in optimizing system performance with respect to user preferences and application requirements, while the modularity of the architecture introduces little overhead. I also explore opportunities that arise from segmenting devices into UI and computational resource components, and show that an automated design environment can be created that greatly simplifies custom device design, reducing time-to-market and lowering costs.&lt;/Abstract>
   	&lt;Abstract>Network devices promise to provide a variety of user interfaces through which users can interact with network applications. The design of these devices stand in stark contrast to the design of personal computers in which new software content is accommodated by increased processor performance. Network device design, on the other hand, must take into consideration a variety of metrics including interactive performance, power consumption, battery life, transaction security, physical size and weight, and cost. Designing a general-purpose platform that caters to all of these metrics for all applications and devices is impractical. For an application mix, a processor architecture and platform can be designed that is optimized for a selected set of metrics, such as power consumption and battery life. Each of these optimized processor architectures and platforms will no doubt be applicable to a variety of devices. This suggests a modular system architecture for network devices that segments the computational resources from the device UI. Computational resources can be selected for a device UI that are optimized with respect to application mixes as well as to user preferences and metrics. Segmenting out the device UI reduces the complexity of device UIs, simplifying development and lowering costs. At the same time, with little electrical circuitry resident on device UIs, the selected platform can more fully optimize the entire device.&lt;/Abstract>
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