2026-09-19T15:03:20Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/270912022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Krste Asanović.
Cheng, Tina, 1980-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-09-06T21:41:45Z
2005-09-06T21:41:45Z
2003
2003
http://hdl.handle.net/1721.1/27091
56821844
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 83).
The complexity of microprocessor chip designs continues to grow with every generation. At the same time, the amount of manpower needed for these projects also continues to grow, creating the need for a better integration flow. Due to this trend, many design conventions are set before the implementation of the chip commences to aid in the integration. This thesis describes the development of a suite of tools which check various design rules in accordance with predefined conventions, in particular the SCALE-0 VLSI design conventions. The tool suite consists of units that check naming conventions, units that check that the design is structural Verilog, and units that check leaf signal rules. A flexible input format for describing the rules is also developed so the tool can be easily adapted for new conventions and new chip designs. The input to the tools is a Verilog design file. Icarus Verilog is modified to parse this Verilog into an XML format. The tool then uses this format, along with the rules that have been defined, as inputs and performs the checks that are specified.
by Tina Cheng.
M.Eng.
83 p.
2801632 bytes
2810534 bytes
application/pdf
application/pdf
en_US
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Sieve : an XML-based structural Verilog rules check tool
XML-based structural Verilog rules check tool
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="a61aea16-96d6-40fc-8629-6008c01a9fe5">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>en_US</Language>
<Title>Sieve : an XML-based structural Verilog rules check tool</Title>
<Subtitle>XML-based structural Verilog rules check tool</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2003</PublicationDate>
<Authors>
<Author>
<DisplayName>Cheng, Tina, 1980-</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>The complexity of microprocessor chip designs continues to grow with every generation. At the same time, the amount of manpower needed for these projects also continues to grow, creating the need for a better integration flow. Due to this trend, many design conventions are set before the implementation of the chip commences to aid in the integration. This thesis describes the development of a suite of tools which check various design rules in accordance with predefined conventions, in particular the SCALE-0 VLSI design conventions. The tool suite consists of units that check naming conventions, units that check that the design is structural Verilog, and units that check leaf signal rules. A flexible input format for describing the rules is also developed so the tool can be easily adapted for new conventions and new chip designs. The input to the tools is a Verilog design file. Icarus Verilog is modified to parse this Verilog into an XML format. The tool then uses this format, along with the rules that have been defined, as inputs and performs the checks that are specified.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>