2026-09-20T13:43:22Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/282712022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Henry I. Smith.
Meinhold, Mitchell W., 1972-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-09-26T19:29:09Z
2005-09-26T19:29:09Z
2003
2003
http://hdl.handle.net/1721.1/28271
53246828
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (leaves 117-118).
Double-gate MOSFETs represent a significant solution to transistor scaling problems and promise a dramatic improvement in both performance and power consumption. In this work, a planar lithographic process is presented that is capable of producing double-gate MOSFET (DGFET) gate structures with 50 nm physical gate length and <5 nm alignment between upper and lower gates. Because a self-aligned approach is not taken, the central challenge in fabrication is to define each gate in separate lithographic steps with precision alignment of upper to lower-gate masks. In order to obtain optimum device performance, the position of the lower-gate should be aligned to the upper-gate to better than 10% of the gate length. The gates are defined using X-ray lithography (a close-proximity shadow printing scheme). The associated alignment scheme, Interferometric Broad Band Imaging (IBBI), has been proven to yield nanometer level sensitivity. While the IBBI alignment system offers superior alignment detectivity, it must be complemented by comparably successful mask pattern placement in order to yield structure details within the desired 5 nm tolerances. This work addresses the details of a novel mask design and fabrication scheme as well as its incorporation into the process flow of the DGFET. Additionally, the parasitic effects of strain that result from wafer bonding and thermal effects have been measured and analyzed.
by Mitchell W. Meinhold.
Ph.D.
118 leaves
17746658 bytes
17760996 bytes
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Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
X-ray lithographic alignment and overlay applied to double-gate MOSFET fabrication
Thesis
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