2026-09-19T10:32:53Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/283802022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Michael H. Perrott.
Crain, Ethan A. (Ethan Alan), 1972-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-09-26T20:08:31Z
2005-09-26T20:08:31Z
2004
2004
http://hdl.handle.net/1721.1/28380
56960521
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 117-118).
A novel offset voltage compensation method is presented that significantly modifies the existing tradeoff between control loop bandwidth, and therefore total compensation time, and total output jitter. The proposed system achieves comparable output jitter performance to traditional approaches while significantly reducing the total compensation time by nearly three orders of magnitude. Traditional offset compensation methods are based on simple offset measurement techniques that generally rely on passive compensation blocks and exhibit a direct inverse relationship between total compensation time and resulting output jitter. Therefore, current high-speed data-link systems suffer from extremely long offset compensation loop settling times in order to satisfy the strict protocol jitter specifications. In the proposed system, the new CMOS peak detector design is the enabling component that allows us break this relationship and achieve extremely fast settling behavior while preventing data dependence of the control signal. Simulated results show that the implemented system can achieve output jitter performance similar to existing methods while dramatically improving the compensation time. Specifically, the proposed system can achieve less than 2pS of peak-to-peak jitter, or less than 700fS of RMS jitter, while reducing the total compensation time from roughly 500[mu]S to less than 1[mu]S. The system was implemented in National Semiconductor's CMOS9 0.18[mu]m CMOS process. Packaged parts will be tested to verify agreement with simulated performance.
by Ethan A. Crain.
M.Eng.
118 p.
6836964 bytes
6851351 bytes
application/pdf
application/pdf
en_US
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Fast offset compensation for a 10Gbps limit amplifier
Thesis
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<Abstract>A novel offset voltage compensation method is presented that significantly modifies the existing tradeoff between control loop bandwidth, and therefore total compensation time, and total output jitter. The proposed system achieves comparable output jitter performance to traditional approaches while significantly reducing the total compensation time by nearly three orders of magnitude. Traditional offset compensation methods are based on simple offset measurement techniques that generally rely on passive compensation blocks and exhibit a direct inverse relationship between total compensation time and resulting output jitter. Therefore, current high-speed data-link systems suffer from extremely long offset compensation loop settling times in order to satisfy the strict protocol jitter specifications. In the proposed system, the new CMOS peak detector design is the enabling component that allows us break this relationship and achieve extremely fast settling behavior while preventing data dependence of the control signal. Simulated results show that the implemented system can achieve output jitter performance similar to existing methods while dramatically improving the compensation time. Specifically, the proposed system can achieve less than 2pS of peak-to-peak jitter, or less than 700fS of RMS jitter, while reducing the total compensation time from roughly 500[mu]S to less than 1[mu]S. The system was implemented in National Semiconductor's CMOS9 0.18[mu]m CMOS process. Packaged parts will be tested to verify agreement with simulated performance.</Abstract>
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