2026-09-19T14:03:07Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/283942026-06-06T01:04:36Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anant Agarwal.
Jakab, Levente, 1981-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-09-26T20:12:53Z
2005-09-26T20:12:53Z
2004
2004
http://hdl.handle.net/1721.1/28394
56978495
Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 203-208).
Recent trends in microprocessor design have moved away from dedicated hardware mechanisms to exposed architectures in which basic functionality is implemented in software. To demonstrate the flexibility of this scheme, I implement a shared memory system on Raw, a tiled multiprocessor. A traditional directory-based cache coherence system is used. The directories are fully resident on several tiles, and the remaining tiles act as users, with cache maintenance routines accessed via interrupt. Previous implementations of shared-memory systems have mostly relied on a combination of dedicated hardware and user-enabled software hooks, with one notable exception, Alewife, combining basic hardware with software support for corner cases. Here, the focus is moved to placing as much support for basic cases into software as possible. The system is designed to minimise custom hardware and user responsibilities. I prove the feasibility of such a design on an exposed architecture such as Raw.
by Levente Jakab.
M.Eng.
S.B.
208 p.
9811968 bytes
9841236 bytes
application/pdf
application/pdf
en_US
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A shared-memory multiprocessor system using the raw tiled architecture
Thesis
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