2026-09-18T22:49:45Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/284072022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Paul Stabler and Christopher J. Terman.
Granich Unikowsky, Adam, 1981-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-09-26T20:16:47Z
2005-09-26T20:16:47Z
2004
2004
http://hdl.handle.net/1721.1/28407
56985448
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaves 108-110).
L dI/dt noise due to simultaneous switching of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant area and can make routing very difficult. The goals of this thesis are twofold: first, to characterize the relationship between noise propagation on chip and parameters such as on-chip resistance and capacitance; and second, to develop an algorithm which will minimize the number of decoupling capacitors on chip while simultaneously reducing the noise to within acceptable boundaries.
by Adam Granich Unikowsky.
M.Eng.
110 leaves
4649741 bytes
4662840 bytes
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Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Allocating decoupling capacitors to reduce simultaneous switching noise on chips
Thesis
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<Abstract>L dI/dt noise due to simultaneous switching of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant area and can make routing very difficult. The goals of this thesis are twofold: first, to characterize the relationship between noise propagation on chip and parameters such as on-chip resistance and capacitance; and second, to develop an algorithm which will minimize the number of decoupling capacitors on chip while simultaneously reducing the noise to within acceptable boundaries.</Abstract>
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