2026-09-18T19:30:39Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/285402022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anant Agarwal.
Taylor, Kenneth William, 1980-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2005-09-27T16:53:47Z
2005-09-27T16:53:47Z
2004
2004
http://hdl.handle.net/1721.1/28540
57396246
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 345-346).
This thesis presents the design and implementation of a 3D graphics pipeline, built on top of the "Raw" processor developed at MIT. The Raw processor consists of a tiled array of CPUs, caches, and routing processors connected by several high-speed networks, and can be treated as a coarse-grained reconfigurable architecture. The graphics pipeline has four stages, and four-way parallelism in each stage, and is mapped on to a 16-tile Raw array. It supports basic rendering functions such as hardware transform and lighting, perspective correct texture mapping, and depth buffering, and is intended to be used as a slave processor receiving rendering commands from a host system. The design process is described in detail, along with difficulties encountered along the way, and a comprehensive performance evaluation is carried out. The paper concludes with many suggestions for architectural and performance improvements to be made over the initial design.
by Kenneth William Taylor.
S.M.
346 p.
15035915 bytes
15082700 bytes
application/pdf
application/pdf
en_US
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture
Thesis
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