2026-09-19T13:12:38Zhttps://dspace.mit.edu/server/oai/request

oai:dspace.mit.edu:1721.1/288432022-01-13T07:54:19Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022

Herbert H. Swain. Rasgon, Stacy A., 1974- Massachusetts Institute of Technology. Dept. of Chemical Engineering. Massachusetts Institute of Technology. Department of Chemical Engineering 2005-09-27T18:39:00Z 2005-09-27T18:39:00Z 2005 2005 http://hdl.handle.net/1721.1/28843 60386212 Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Chemical Engineering, 2005. Includes bibliographical references. (cont.) micromasking. Porous films seem especially prone, perhaps due to polymer diffusion into the pore structure. Control of polymerization during the etch through the use of lower-polymerizing fluorocarbons or the addition of oxygen was shown to effectively control excessive roughening on solid films, while porous dielectrics remain challenging. Finally, an inductively-coupled plasma beam source was used to conduct a preliminary investigation into roughening of polysilicon in an HBr plasma beam. The initial polysilicon topography was shown to seed striation formation at glancing ion incident angles due to scattering and ion shadowing. These results indicate that, in a pure etching process (no deposition) the surface topography can be an important source of roughness and striation formation on sidewalls. For the patterning of sub 100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, both from a fundamental as well as a manufacturing perspective. Until recently, LER studies have focused on the analysis of top-down SEM micrographs of post-developed photoresist lines. However, the effect of plasma etch on sidewall roughness has not received sufficient attention. Plasma etching processes often roughen the feature sidewalls, leading to the formation of anisotropic striations. It is this post-etch sidewall roughness which will ultimately affect device performance. Sidewall roughness transfer through all layers of a process stack (photoresist, ARC/hardmask, and oxide) was observed by cleaving dense line/space patterns parallel to the lines, and directly scanning the exposed sidewall with an atomic force microscope. This technique vividly highlighted the structural nature of the post-etch sidewall, and allowed the extraction of quantitative roughness data as a function of depth. Sidewall roughness transfer can be improved through a variety of processing and material solutions. Maintaining a smooth sidewall immediately prior to the substrate etch (for example, through modulation of the ARC/hardmask open chemistry) leads to smoother sidewalls after oxide or polysilicon etch. However, smoothing must typically be balanced against critical dimension control. Additionally, the resist platform can add to roughness transfer. Thin and/or fluorinated photoresist can enhance roughness due to the poorer etch resistance of these materials. Low-k (OSG) and porous low-k (MSQ) dielectrics can suffer from enhanced roughening during etching in fluorocarbon plasmas due to by Stacy A. Rasgon. Ph.D. 197 p. 11820893 bytes 11846233 bytes application/pdf application/pdf en_US Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Chemical Engineering. Origin, evolution, and control of sidewall line edge roughness transfer during plasma etching Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="75e9fa0f-571d-4855-9dea-2835f47d5f42"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>en_US</Language> <Title>Origin, evolution, and control of sidewall line edge roughness transfer during plasma etching</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2005</PublicationDate> <Authors> <Author> <DisplayName>Rasgon, Stacy A., 1974-</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Chemical Engineering.</Keyword> <Abstract>(cont.) micromasking. Porous films seem especially prone, perhaps due to polymer diffusion into the pore structure. Control of polymerization during the etch through the use of lower-polymerizing fluorocarbons or the addition of oxygen was shown to effectively control excessive roughening on solid films, while porous dielectrics remain challenging. Finally, an inductively-coupled plasma beam source was used to conduct a preliminary investigation into roughening of polysilicon in an HBr plasma beam. The initial polysilicon topography was shown to seed striation formation at glancing ion incident angles due to scattering and ion shadowing. These results indicate that, in a pure etching process (no deposition) the surface topography can be an important source of roughness and striation formation on sidewalls.</Abstract> <Abstract>For the patterning of sub 100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, both from a fundamental as well as a manufacturing perspective. Until recently, LER studies have focused on the analysis of top-down SEM micrographs of post-developed photoresist lines. However, the effect of plasma etch on sidewall roughness has not received sufficient attention. Plasma etching processes often roughen the feature sidewalls, leading to the formation of anisotropic striations. It is this post-etch sidewall roughness which will ultimately affect device performance. Sidewall roughness transfer through all layers of a process stack (photoresist, ARC/hardmask, and oxide) was observed by cleaving dense line/space patterns parallel to the lines, and directly scanning the exposed sidewall with an atomic force microscope. This technique vividly highlighted the structural nature of the post-etch sidewall, and allowed the extraction of quantitative roughness data as a function of depth. Sidewall roughness transfer can be improved through a variety of processing and material solutions. Maintaining a smooth sidewall immediately prior to the substrate etch (for example, through modulation of the ARC/hardmask open chemistry) leads to smoother sidewalls after oxide or polysilicon etch. However, smoothing must typically be balanced against critical dimension control. Additionally, the resist platform can add to roughness transfer. Thin and/or fluorinated photoresist can enhance roughness due to the poorer etch resistance of these materials. Low-k (OSG) and porous low-k (MSQ) dielectrics can suffer from enhanced roughening during etching in fluorocarbon plasmas due to</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>