2026-09-19T04:46:05Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/297322022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Jonathan H. Raymond and Donald E. Troxel.
Maurer, Jennifer (Jennifer Robin), 1979-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-03-24T16:20:19Z
2006-03-24T16:20:19Z
2003
2003
http://hdl.handle.net/1721.1/29732
54040069
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (leaves 97-98).
This project implements a hardware solution to the Advanced Encryption Standard (AES) algorithm and interfaces to IBM's CoreConnect Bus Architecture. The project is IBM SoftCore compliant, is synthesized to the .18 micron CMOS double-well technology, runs at 133 MHz, and is approximately 706K for the 16x128 bit buffer implementation and 874K gates for the 32x128 bit buffer implementation. Data can be encrypted and decrypted at a throughput of 1Gbps. The work described in the paper was completed as a part of MIT's VI-A program in the ASIC Digital Cores III group of the Microelectronics Division at IBM.
by Jennifer Maurer.
M.Eng.
98 leaves
3092988 bytes
3092797 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Hardware implementation of the Advanced Encryption Standard
Hardware implementation of the AES
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="756cc740-c42a-422f-a111-eba6969c78e6">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>Hardware implementation of the Advanced Encryption Standard</Title>
<Subtitle>Hardware implementation of the AES</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2003</PublicationDate>
<Authors>
<Author>
<DisplayName>Maurer, Jennifer (Jennifer Robin), 1979-</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>This project implements a hardware solution to the Advanced Encryption Standard (AES) algorithm and interfaces to IBM's CoreConnect Bus Architecture. The project is IBM SoftCore compliant, is synthesized to the .18 micron CMOS double-well technology, runs at 133 MHz, and is approximately 706K for the 16x128 bit buffer implementation and 874K gates for the 32x128 bit buffer implementation. Data can be encrypted and decrypted at a throughput of 1Gbps. The work described in the paper was completed as a part of MIT's VI-A program in the ASIC Digital Cores III group of the Microelectronics Division at IBM.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>