2026-09-19T05:49:03Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/301742022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Arvind.
Dave, Nirav Hemant, 1982-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-03-24T18:26:27Z
2006-03-24T18:26:27Z
2005
2005
http://hdl.handle.net/1721.1/30174
60678546
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 67).
In this thesis, we designed a 2-way out-of-order processor in Bluespec implementing the MIPS I integer ISA. A number of scheduling optimizations were then used to bring the initial design up to the same level of cycle-level concurrency as found in standard RTL-level designs. From this, a general design methodology is proposed to effectively express, debug, and optimize large Bluespec designs.
by Nirav Hemant Dave.
S.M.
67 p.
2477069 bytes
2483761 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Designing a processor in Bluespec
Thesis
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