2026-09-19T15:03:32Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/303702022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Lawrence De Vito and Anantha P. Chandrakasan.
Brasca, Claudio M. E
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-03-21T21:09:11Z
2006-03-21T21:09:11Z
2004
2004
http://hdl.handle.net/1721.1/30370
62239329
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 102-104).
Clock buffers constitute a major source of power dissipation in VLSI circuits. In CMOS the load is primarily capacitive and hence an inductive shunt can reduce real power needs. This almost-adiabatic topology is referred to as a resonant buffer. Two resonant buffers can be actively controlled by additional variable capacitance, to deliver quadrature signals from a single incoming clock. The cost of this quadrature generation is added complexity of control algorithm and the advantage is 85% less power than alternate methods. This topology is used to create quadrature signals and drive the clock inputs of a bang-bang half-rate phase detector in a 10GBit/sec Clock and Data Recovery Circuit. The 0.13um CMOS implementation shows significant power savings. A useful closed form expression for jitter transfer characteristic of generic linear-time-invariant filters is derived and applied to the proposed buffer to show it can be transparently integrated in existing CDR architectures. The work for this thesis was conducted in part at Analog Devices Inc.
by Claudio M.E. Brasca.
M.Eng.
104 leaves
966301 bytes
929309 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
5GHz CMOS resonant clock buffer with quadrature generation for fiber optic applications
Five gigahertz complementary metal oxide semiconductor resonant clock buffer with quadrature generation for fiber optic applications
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="42cb60cb-dce0-436f-9a81-2b36a541e8aa">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>5GHz CMOS resonant clock buffer with quadrature generation for fiber optic applications</Title>
<Subtitle>Five gigahertz complementary metal oxide semiconductor resonant clock buffer with quadrature generation for fiber optic applications</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2004</PublicationDate>
<Authors>
<Author>
<DisplayName>Brasca, Claudio M. E</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>Clock buffers constitute a major source of power dissipation in VLSI circuits. In CMOS the load is primarily capacitive and hence an inductive shunt can reduce real power needs. This almost-adiabatic topology is referred to as a resonant buffer. Two resonant buffers can be actively controlled by additional variable capacitance, to deliver quadrature signals from a single incoming clock. The cost of this quadrature generation is added complexity of control algorithm and the advantage is 85% less power than alternate methods. This topology is used to create quadrature signals and drive the clock inputs of a bang-bang half-rate phase detector in a 10GBit/sec Clock and Data Recovery Circuit. The 0.13um CMOS implementation shows significant power savings. A useful closed form expression for jitter transfer characteristic of generic linear-time-invariant filters is derived and applied to the proposed buffer to show it can be transparently integrated in existing CDR architectures. The work for this thesis was conducted in part at Analog Devices Inc.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>