<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T03:02:46Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/33115" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/33115</identifier><datestamp>2022-01-13T07:54:29Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131023</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Frédo Durand.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Chen, Jiawen (Jiawen Kevin)</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2006-06-19T17:42:00Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2006-06-19T17:42:00Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2005</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2005</dim:field>
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   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">62233328</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (p. 77-80).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">Commodity graphics hardware has become increasingly programmable over the last few years, but has been limited to a fixed resource allocation. These architectures handle some workloads well, others poorly; load-balancing to maximize graphics hardware performance has become a critical issue. I have designed a system that solves the load-balancing problem in real-time graphics by using compile-time resource allocation on general-purpose hardware. I implemented a flexible graphics pipeline on Raw, a tile-based multicore processor. The complete graphics pipeline is expressed using StreamIt, a high-level language based on the stream programming model. The StreamIt compiler automatically maps the stream computation onto the Raw architecture. The system is evaluated by comparing the performance of the flexible pipeline with a fixed allocation representative of commodity hardware on common rendering tasks. The benchmarks place workloads on different parts of the pipeline to determine the effectiveness of the load-balance. The flexible pipeline achieves up to twice the throughput of a static allocation.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Jiawen Chen.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">M.Eng.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">80 p.</dim:field>
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   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.</dim:field>
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   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Load-balanced rendering on a general-purpose tiled architecture</dim:field>
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   	&lt;Title>Load-balanced rendering on a general-purpose tiled architecture&lt;/Title>
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   	&lt;PublicationDate>2005&lt;/PublicationDate>
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    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>Commodity graphics hardware has become increasingly programmable over the last few years, but has been limited to a fixed resource allocation. These architectures handle some workloads well, others poorly; load-balancing to maximize graphics hardware performance has become a critical issue. I have designed a system that solves the load-balancing problem in real-time graphics by using compile-time resource allocation on general-purpose hardware. I implemented a flexible graphics pipeline on Raw, a tile-based multicore processor. The complete graphics pipeline is expressed using StreamIt, a high-level language based on the stream programming model. The StreamIt compiler automatically maps the stream computation onto the Raw architecture. The system is evaluated by comparing the performance of the flexible pipeline with a fixed allocation representative of commodity hardware on common rendering tasks. The benchmarks place workloads on different parts of the pipeline to determine the effectiveness of the load-balance. The flexible pipeline achieves up to twice the throughput of a static allocation.&lt;/Abstract>
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