2026-09-21T13:30:32Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/331402026-06-06T01:04:41Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Karen Pieper and Arvind.
Dong, Wenyan, 1980-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-06-19T17:44:46Z
2006-06-19T17:44:46Z
2004
2004
http://hdl.handle.net/1721.1/33140
62242432
Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaves 62-63).
This thesis presents a research project on decoder related optimizations in HDL de- signs. The goal of the research is to improve design synthesis quality-of-result, mainly in terms of area; this involves sharing decoders driven by related inputs, and map decoders using fewer number of boolean gates. Algorithms presented in this thesis were implemented in the Presto HDL compiler. A series of tests were conducted using real-world HDL designs in order to determine how effective these optimizations are.
by Wenyan Dong.
M.Eng.
S.B.
63 leaves
2956534 bytes
2958300 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Improved handling of the decoding operation in the Presto compiler
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="ff77959f-2c38-4ac2-9b5d-de763e8c770d">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>Improved handling of the decoding operation in the Presto compiler</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2004</PublicationDate>
<Authors>
<Author>
<DisplayName>Dong, Wenyan, 1980-</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>This thesis presents a research project on decoder related optimizations in HDL de- signs. The goal of the research is to improve design synthesis quality-of-result, mainly in terms of area; this involves sharing decoders driven by related inputs, and map decoders using fewer number of boolean gates. Algorithms presented in this thesis were implemented in the Presto HDL compiler. A series of tests were conducted using real-world HDL designs in order to determine how effective these optimizations are.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>